DNA STRUCTURAL FEATURES AND ARCHITECTURE OF PROMOTER REGIONS PLAY A ROLE IN GENE RESPONSIVENESS OF S. CEREVISIAE

Gene expression is the most fundamental biological process, which is essential for phenotypic variation. It is regulated by various external (environment and evolution) and internal (genetic) factors. The level of gene expression depends on promoter architecture, along with other external factors. Presence of sequence motifs, such as transcription factor binding sites (TFBSs) and TATA-box, or DNA methylation in vertebrates has been implicated in the regulation of expression of some genes in eukaryotes, but a large number of genes lack these sequences. On the other hand, several experimental and computational studies have shown that promoter sequences possess some special structural properties, such as low stability, less bendability, low nucleosome occupancy, and more curvature, which are prevalent across all organisms. These structural features may play role in transcription initiation and regulation of gene expression. We have studied the relationship between the structural features of promoter DNA, promoter directionality and gene expression variability in S. cerevisiae. This relationship has been analyzed for seven different measures of gene expression variability, along with two different regulatory effect measures. We find that a few of the variability measures of gene expression are linked to DNA structural properties, nucleosome occupancy, TATA-box presence, and bidirectionality of promoter regions. Interestingly, gene responsiveness is most intimately correlated with DNA structural features and promoter architecture.

Design of a Low Power 64 Point FFT Architecture for WLAN Applications

This paper presents a Radix-4(3) based FFT architecture suitable for OFDM based WLAN applications. The radix-4(3) parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm(2). The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.

Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

An 8 × 8 pipelined parallel multiplier which uses the Dadda scheme is presented. The multiplier has been implemented in a 3-μm n-well CMOS process with two layers of metal using a standard cell automatic placement and routing program. The design uses a form of pipelined carry look-ahead adder in the final stage of summation, thus providing a significant contribution to the high performance of the multiplier. The design is expected to operate at a clock frequency of at least 50 MHz and has a flush time of seven clock cycles. The design illustrates a possible method of implementing an irregular architecture in VLSI using multiple levels of low-resistance, low-capacitance interconnect and automated layout techniques.

Characterization of the sleep architecture in two species of fruit bat

Bats (Chiroptera) are the second-most abundant mammalian order in the world, occupying a diverse range of habitats and exhibiting many different life history traits. In order to contribute to this highly underrepresented group we describe the sleep architecture of two species of frugivorous bat, the greater short-nosed fruit bat (Cynopterus sphinx) and the lesser dawn fruit bat (Eonycteris spelaea). Electroencephalogram (EEG) and electromyogram (EMG) data were recorded from multiple individuals (>= 5) by telemetry over a 72-h period in a laboratory setting with light/dark cycles equivalent to those found in the wild. Our results show that over a 24-h period both species spent more time asleep than awake (mean 15 h), less than previous reported for Chiroptera (20 h). C sphinx spent significantly more of its non-rapid eye movement sleep (NREM) and rapid eye movement sleep (REM) quotas during the light phase, while E. spelaea divided its sleep-wake architecture equally between both light and dark phases. Comparing the sleep patterns of the two species found that C. sphinx had significantly fewer NREM and REM episodes than E. spelaea but each episode lasted for a significantly longer period of time. Potential hypotheses to explain the differences in the sleep architecture of C. sphinx with E. spelaea, including risk of predation and social interaction are discussed. (C) 2010 Published by Elsevier B.V.

A Complex BPF with On Chip Auto-tuning Architecture for Wireless Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18um standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 16.2dBm, with 50 Omega as the source impedance. The input referred noise is about 80uV(rms). The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28 x 0.22 mm(2), less than 1/8 of that of the main-filter which is 0.92 x 0.59 mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A Complex BPF with On Chip Auto-tuning Architecture for Low-IF Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18 mu m standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 19dBm, with 50 Omega as the source impedance. The input referred noise is about 80 mu V-rms. The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28x0.22mm(2), less than 1/8 of that of the main-filter which is 0.92x0.59mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

Performance of an embedded optical vector matrix multiplication processor architecture

An embedded architecture of optical vector matrix multiplier (OVMM) is presented. The embedded architecture is aimed at optimising the data flow of vector matrix multiplier (VMM) to promote its performance. Data dependence is discussed when the OVMM is connected to a cluster system. A simulator is built to analyse the performance according to the architecture. According to the simulation, Amdahl's law is used to analyse the hybrid opto-electronic system. It is found that the electronic part and its interaction with optical part form the bottleneck of system.

Response of chlorophyll fluorescence to dynamic light in three alpine species differing in plant architecture

A study was carried out to examine the effect of dynamic photosynthetically active photon flux density (PPFD) on photoinhibition and energy use in three herbaceous species, prostrate Saussurea superba, erect-leaved S. katochaete, and half-erect-leaved Gentiana straminea, from the Qinghai-Tibet Plateau. Chlorophyll fluorescence response was measured under each of three sets of high-low PPFD combinations: 1700-0, 1400-300, and 1200-500 mu mol m(-2) s(-1), illuminating in four dynamic frequencies: 1, 5, 15, and 60 cycles per 2 h. The total light exposure time was 2h and the integrated PPFD was the same in all treatments. The highest frequency of PPFD fluctuation resulted in the lowest photochemical activity, the highest level of non-photochemical quenching, and the greatest decrease of F-v/F-m (maximal photochemical efficiency of PSII). The 5 and 15 cycles per 2h treatments resulted in higher photochemical activity than the 1 cycle per 2h treatment. The 1700-0 PPFD combination led to the lowest photochemical activity and more serious photoinhibition in all species. S. superba usually exhibited the highest photochemical activity and CO2 uptake rate, the lowest reduction of F-v/F-m,F- and the smallest fraction of energy in thermal dissipation. With similar fractions of thermal dissipation, S. katochaete had relatively less photoinhibition than G. straminea owing to effective F-o quenching. The results suggest that high frequency of fluctuating PPFD generally results in photoinhibition, which is more serious under periods of irradiation with high light intensity. (c) 2005 Elsevier B.V. All rights reserved.

Technology and the architecture of markets: re-configuring the Canadian equity market

This paper examines the relation between technical possibilities, liberal logics, and the concrete reconfiguration of markets. It focuses on the enrolling of innovations in communication and information technologies into the markets traditionally dominated by stock exchanges. With the development of capacities to trade on-screen, the power of incumbent market makers has been challenged as a less stable array of competing quasi-public and private marketplaces emerges. Developing a case study of the Toronto Stock Exchange, I argue that narrative emphasis on the performative power of sociotechnical innovations, the deterritorialisation of financial relations, and the erosion of state capacities needs qualification. A case is made for the importance of developing an understanding of: the spaces of encounter between emerging social technologies and property rights, rules of exchange, and structures of governance; and the interplay of orderings of different institutional composition and spatial reach in the reconfiguration of market architectures. Only then can a better grasp be gained of the evolving dynamics between making markets, the regulatory powers of the state, and their delimitations.

Process-variation resilient and voltage-scalable dct architecture for robust low-power computing

In this paper, we present a novel discrete cosine transform (DCT) architecture that allows aggressive voltage scaling for low-power dissipation, even under process parameter variations with minimal overhead as opposed to existing techniques. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors appear only from the long paths that are designed to be less contributive to output quality. The proposed architecture allows a graceful degradation in the peak SNR (PSNR) under aggressive voltage scaling as well as extreme process variations. Results show that even under large process variations (±3σ around mean threshold voltage) and aggressive supply voltage scaling (at 0.88 V, while the nominal voltage is 1.2 V for a 90-nm technology), there is a gradual degradation of image quality with considerable power savings (71% at PSNR of 23.4 dB) for the proposed architecture, when compared to existing implementations in a 90-nm process technology. © 2006 IEEE.

Process variation tolerant low power DCT architecture

2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive voltage scaling by exploiting the fact that not all intermediate computations are equally important in a DCT system to obtain "good" image quality with Peak Signal to Noise Ratio(PSNR) > 30 dB. This observation has led us to propose a DCT architecture where the signal paths that are less contributive to PSNR improvement are designed to be longer than the paths that are more contributive to PSNR improvement. It should also be noted that robustness with respect to parameter variations and low power operation typically impose contradictory requirements in terms of architecture design. However, the proposed architecture lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors would only appear from the long paths that are less contributive towards PSNR improvement, providing large improvement in power dissipation with small PSNR degradation. Results show that even under large process variation and supply voltage scaling (0.8V), there is a gradual degradation of image quality with considerable power savings (62.8%) for the proposed architecture when compared to existing implementations in 70 nm process technology.

Pilot tone reference-less phase conjugator for phase modulated retrodirective antenna applications

This letter presents a simple tracking phased locked loop (PLL) that can be used to track phase-modulated signals and provide a phase-conjugated signal for retrodirective retransmission. The configuration allows the retrodirective antenna to directly track phase-modulated signals with no requirement for a separate continuous wave (CW) pilot tone. The ability to directly track phase-modulated signals is carried out using a 4× multiplier on the tracking PLL reference signal. Practical phase conjugation results are presented for a five-element retrodirective array simultaneously sending and receiving phase-modulated (QPSK) signals. Signals with levels as low as -122 dBm can be phase-conjugated and retransmitted with 30 dBm EIRP.

Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE

Homomorphic encryption offers potential for secure cloud computing. However due to the complexity of homomorphic encryption schemes, performance of implemented schemes to date have been unpractical. This work investigates the use of hardware, specifically Field Programmable Gate Array (FPGA) technology, for implementing the building blocks involved in somewhat and fully homomorphic encryption schemes in order to assess the practicality of such schemes. We concentrate on the selection of a suitable multiplication algorithm and hardware architecture for large integer multiplication, one of the main bottlenecks in many homomorphic encryption schemes. We focus on the encryption step of an integer-based fully homomorphic encryption (FHE) scheme. We target the DSP48E1 slices available on Xilinx Virtex 7 FPGAs to ascertain whether the large integer multiplier within the encryption step of a FHE scheme could fit on a single FPGA device. We find that, for toy size parameters for the FHE encryption step, the large integer multiplier fits comfortably within the DSP48E1 slices, greatly improving the practicality of the encryption step compared to a software implementation. As multiplication is an important operation in other FHE schemes, a hardware implementation using this multiplier could also be used to improve performance of these schemes.

Continental margin architecture : the palynological signature of glacioeustasy /

Palynomorphs from two siliciclastic margins were examined to gain insights into continental margin architecture. Sea level change is thought to be one of the primary controls on continental margin architecture. Because Late Neogene glacioeustasy has been well studied marine sediments deposited during the Late Neogene were examined to test this concept. Cores from the outer shelf and upper slope were taken from the New Jersey margin in the western North Atlantic Ocean and from the Sunda Shelf margin in the South China Sea. Continental margin architecture is often described in a sequence stratigraphic context. One of the main goals of both coring projects was to test the theoretical sequence stratigraphic models developed by a research group at Exxon (e.g. Wilgus et al., 1988). Palynomorphs provide one of the few methods of inferring continental margin architecture in monotonous, siliciclastic marine sediments where calcareous sediments are rare (e.g. New Jersey margin). In this study theoretical models of the palynological signature expected in sediment packages deposited during the various increments of a glacioeustatic cycle were designed. These models were based on the modem palynomorph trends and taphonomic factors thought to control palynomorph distribution. Both terrestrial (pollen and spores) and marine (dinocysts) palynomorphs were examined. The palynological model was then compared with New Jersey margin and Sunda Shelf margin sediments. The predicted palynological trends provided a means of identifying a complete cycle of glacioeustatic change (Oxygen Isotope Stage 5e to present) in the uppermost 80 meters of sediment on the slope at the New Jersey margin. Sediment availability, not sea meters of sediment on the slope at the New Jersey margin. Sediment availability, not sea level change, is thought to be the major factor controlling margin architecture during the late Pleistocene here at the upper slope. This is likely a function of the glacial scouring of the continents which significantly increases sediment availability during glacial stages. The subaerially exposed continental shelf during the lowstand periods would have been subject to significant amounts of erosion fi:om the proglacial rivers flowing fi-om the southern regions of the ice-sheet. The slope site is non-depositional today and was also non-depositional during the last full interglacial period. The palynomorph data obtained fi-om the South China Sea indicate that the major difference between the New Jersey Margin sites and the Sunda Shelf margin sites is the variation in sediment supply and the rate of sediment accumulation. There was significantly less variation in sediment supply between glacial and interglacial periods and less overall sediment accumulation at the Sunda Shelf margin. The data presented here indicate that under certain conditions the theoretical palynological models allow the identification of individual sequence stratigraphic units and therefore, allow inferences regarding continental margin architecture. The major condition required in this approach is that a complete and reliable database of the contemporaneous palynomorphs be available.

Rebuilding less vulnerable communities : the case of Holy Cross

La résilience est la capacité à s’adapter aux menaces et à atténuer ou éviter un risque, elle peut être trouvée dans des bâtiments résistant aux dangers ou dans des systèmes sociaux adaptables (Pelling, 2003). Par conséquence, ce concept peut aussi être compris comme la capacité de reconstruire un quartier avec des composants plus solides et plus viables. Presque quatre ans après l’ouragan Katrina, la Nouvelle-Orléans est considérée comme un laboratoire à ciel ouvert. Le niveau de résilience de ses communautés peut y être examiné. L’état actuel de la reconstitution de ses quartiers diffère largement des uns aux autres. L’arrondissement historique de Holy Cross est l’un des plus vieux quartiers de la ville, cette communauté vulnérable est connue pour son patrimoine culturel, apparent non seulement dans son architecture unique, mais aussi ses relations sociales. Un des principaux défi de la reconstruction du quartier de Holly Cross est de trouver une façon de concilier la préservation du patrimoine bâti et de son tissu urbain ancien avec de nouveaux plans de développement, afin de créer une communauté durable. Cette étude examine les rôles des acteurs impliqués dans le processus de reconstruction et leur efficacité sur la création d’un Holy Cross plus durable, résistant et abordable, afin d’encourager le retour de ses résidents. Elle présente également les efforts actuels pour proposer des projets de reconstruction durables tout en préservant le caractère patrimonial du quartier.