Multiplier-less realization of a poly-phase filter using LUT-based FPGAs

In DSP applications such as fixed transforms and filtering, the full flexibility of a general-purpose multiplier is not required and only a limited range of values is needed on one of the multiplier inputs. A new design technique has been developed for deriving multipliers that operate on a limited range of multiplicands. This can be used to produce FPGA implementations of DSP systems where area is dramatically improved. The paper describes the technique and its application to the design of a poly-phase filter on a Virtex FPGA. A 62% area reduction and 7% speed increase is gained when compared to an equivalent design using general purpose multipliers. It is also compared favourably to other known fixed coefficient approaches.

When is the second local multiplier algebra of a C*-algebra equal to the first?

We discuss necessary as well as sufficient conditions for the second iterated local multiplier algebra of a separable C*-algebra to agree with the first.

COMPLETELY ITERATIVE, PIPELINED MULTIPLIER ARRAY SUITABLE FOR VLSI.

A pipelined array multiplier which has been derived by applying 'systolic array' principles at the bit level is described. Attention is focused on a circuit which is used to multiply streams of parallel unsigned data. Then an algorithm is given which demonstrates that, with only a simple modification to the basic cell, the same array can cope with two's complement numbers. The resulting structure has a number of features whch make it attractive to LSI and VLSI. These include regularity and modularity.

Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE

Homomorphic encryption offers potential for secure cloud computing. However due to the complexity of homomorphic encryption schemes, performance of implemented schemes to date have been unpractical. This work investigates the use of hardware, specifically Field Programmable Gate Array (FPGA) technology, for implementing the building blocks involved in somewhat and fully homomorphic encryption schemes in order to assess the practicality of such schemes. We concentrate on the selection of a suitable multiplication algorithm and hardware architecture for large integer multiplication, one of the main bottlenecks in many homomorphic encryption schemes. We focus on the encryption step of an integer-based fully homomorphic encryption (FHE) scheme. We target the DSP48E1 slices available on Xilinx Virtex 7 FPGAs to ascertain whether the large integer multiplier within the encryption step of a FHE scheme could fit on a single FPGA device. We find that, for toy size parameters for the FHE encryption step, the large integer multiplier fits comfortably within the DSP48E1 slices, greatly improving the practicality of the encryption step compared to a software implementation. As multiplication is an important operation in other FHE schemes, a hardware implementation using this multiplier could also be used to improve performance of these schemes.

L'art de fabriquer le salin et la potasse ; suivi des Expériences sur les moyens de multiplier la fabrication de la potasse ([Reprod.]) / par le citoyen Pertuis, & par le citoyen B. G. Sage...

Collection : Les archives de la Révolution française ; 10.3.38

Decimal Multiplication using compact BCD Multiplier

Decimal multiplication is an integral part offinancial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 x 4 multiplication, combinations need x multiplication, and the remaining combinations use either x or x 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation ofpartial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit x n-digit) multiplication.

Performance analysis of double digit decimal multiplier on various FPGA logic families

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that performs 2 digit multiplications simultaneously in one clock cycle. This design offers low latency and high throughput. When multiplying two n-digit operands to produce a 2n-digit product, the design has a latency of (n / 2) 1 cycles. The paper presents area and delay comparisons for 7-digit, 16-digit, 34-digit double digit decimal multipliers on different families of Xilinx, Altera, Actel and Quick Logic FPGAs. The multipliers presented can be extended to support decimal floating-point multiplication for IEEE P754 standard

High performance, low latency double digit decimal multiplier on ASIC and FPGA

Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.

Revisiting the US money demand function: an application of the Lagrange multiplier structural break unit root test and the bounds test for a long-run relationship

In this article, we examine the issue of a levels relationship and stability of the US money demand function over the period 1959:01 to 2004:02. We use the Lagrange multiplier structural break unit root test and the bounds testing approach to a long-run relationship in levels of the variables, namely real money demand, nominal interest rate and real income. We find greater evidence for a long-run relationship in levels and stability of the US money demand function when we use M2 as a proxy for money demand. However, we find little evidence for a long-run relationship between M1 and M2 with their determinants for the recent period, spanning the last decade or so.

Are bilateral real exchange rates stationary? Evidence from Lagrange multiplier unit root tests for India

The paper examines the stationarity of India’s real exchange rate vis-a` -vis 16 of its major trading partner countries for the period 1960–2000. Application of the conventional ADF unit root test, the Lagrange multiplier (LM) unit root test with one structural break, and the LM unit root test with two structural breaks provides evidence that India’s exchange rate vis-a` -vis 15 out of 16 countries is stationary, implying support for purchasing power parity.

Comparing the small sample properties of two break Lagrange Multiplier unit root tests

In this note, we examine the size and power properties and the break date estimation accuracy of the Lee and Strazicich (LS, 2003) two break endogenous unit root test, based on two different break date selection methods: minimising the test statistic and minimising the sum of squared residuals (SSR). Our results show that the performance of both Models A and C of the LS test are superior when one uses the minimising SSR procedure.