619 resultados para Multiplication
Resumo:
Decimal multiplication is an integral part offinancial, commercial, and internet-based computations. The basic building block of a decimal multiplier is a single digit multiplier. It accepts two Binary Coded Decimal (BCD) inputs and gives a product in the range [0, 81] represented by two BCD digits. A novel design for single digit decimal multiplication that reduces the critical path delay and area is proposed in this research. Out of the possible 256 combinations for the 8-bit input, only hundred combinations are valid BCD inputs. In the hundred valid combinations only four combinations require 4 x 4 multiplication, combinations need x multiplication, and the remaining combinations use either x or x 3 multiplication. The proposed design makes use of this property. This design leads to more regular VLSI implementation, and does not require special registers for storing easy multiples. This is a fully parallel multiplier utilizing only combinational logic, and is extended to a Hex/Decimal multiplier that gives either a decimal output or a binary output. The accumulation ofpartial products generated using single digit multipliers is done by an array of multi-operand BCD adders for an (n-digit x n-digit) multiplication.
Resumo:
Decimal multiplication is an integral part of financial, commercial, and internet-based computations. A novel design for single digit decimal multiplication that reduces the critical path delay and area for an iterative multiplier is proposed in this research. The partial products are generated using single digit multipliers, and are accumulated based on a novel RPS algorithm. This design uses n single digit multipliers for an n × n multiplication. The latency for the multiplication of two n-digit Binary Coded Decimal (BCD) operands is (n + 1) cycles and a new multiplication can begin every n cycle. The accumulation of final partial products and the first iteration of partial product generation for next set of inputs are done simultaneously. This iterative decimal multiplier offers low latency and high throughput, and can be extended for decimal floating-point multiplication.
Resumo:
Pseudomonas syringae pv. phaseolicola is the seed borne causative agent of halo blight in the common bean Phaseolus vulgaris. Pseudomonas syringae pv. phaseolicola race 4 strain 1302A contains the avirulence gene hopAR1 (located on a 106-kb genomic island, PPHGI-1, and earlier named avrPphB), which matches resistance gene R3 in P. vulgaris cultivar Tendergreen (TG) and causes a rapid hypersensitive reaction (HR). Here, we have fluorescently labeled selected Pseudomonas syringae pv. phaseolicola 1302A and 1448A strains (with and without PPHGI-1) to enable confocal imaging of in-planta colony formation within the apoplast of resistant (TG) and susceptible (Canadian Wonder [CW]) P. vulgaris leaves. Temporal quantification of fluorescent Pseudomonas syringae pv. phaseolicola colony development correlated with in-planta bacterial multiplication (measured as CFU/ml) and is, therefore, an effective means of monitoring Pseudomonas syringae pv. phaseolicola endophytic colonization and survival in P. vulgaris. We present advances in the application of confocal microscopy for in-planta visualization of Pseudomonas syringae pv. phaseolicola colony development in the leaf mesophyll to show how the HR defense response greatly affects colony morphology and bacterial survival. Unexpectedly, the presence of PPHGI-1 was found to cause a reduction of colony development in susceptible P. vulgaris CW leaf tissue. We discuss the evolutionary consequences that the acquisition and retention of PPHGI-1 brings to Pseudomonas syringae pv. phaseolicola in planta.
Resumo:
Simultaneous observations of cloud microphysical properties were obtained by in-situ aircraft measurements and ground based Radar/Lidar. Widespread mid-level stratus cloud was present below a temperature inversion (~5 °C magnitude) at 3.6 km altitude. Localised convection (peak updraft 1.5 m s−1) was observed 20 km west of the Radar station. This was associated with convergence at 2.5 km altitude. The convection was unable to penetrate the inversion capping the mid-level stratus.
The mid-level stratus cloud was vertically thin (~400 m), horizontally extensive (covering 100 s of km) and persisted for more than 24 h. The cloud consisted of supercooled water droplets and small concentrations of large (~1 mm) stellar/plate like ice which slowly precipitated out. This ice was nucleated at temperatures greater than −12.2 °C and less than −10.0 °C, (cloud top and cloud base temperatures, respectively). No ice seeding from above the cloud layer was observed. This ice was formed by primary nucleation, either through the entrainment of efficient ice nuclei from above/below cloud, or by the slow stochastic activation of immersion freezing ice nuclei contained within the supercooled drops. Above cloud top significant concentrations of sub-micron aerosol were observed and consisted of a mixture of sulphate and carbonaceous material, a potential source of ice nuclei. Particle number concentrations (in the size range 0.1
Resumo:
Let C be a smooth, absolutely irreducible genus 3 curve over a number field M. Suppose that the Jacobian of C has complex multiplication by a sextic CM-field K. Suppose further that K contains no imaginary quadratic subfield. We give a bound on the primes p of M such that the stable reduction of C at p contains three irreducible components of genus 1.
Resumo:
An accurate switched-current (SI) memory cell and suitable for low-voltage low-power (LVLP) applications is proposed. Information is memorized as the gate-voltage of the input transistor, in a tunable gain-boosting triode-transconductor. Additionally, four-quadrant multiplication between the input voltage to the transconductor regulation-amplifier (X-operand) and the stored voltage (Y-operand) is provided. A simplified 2 x 2-memory array was prototyped according to a standard 0.8 mum n-well CMOS process and 1.8-V supply. Measured current-reproduction error is less than 0.26% for 0.25 muA less than or equal to I-SAMPLE less than or equal to 0.75 muA. Standby consumption is 6.75 muW per cell @I-SAMPLE = 0.75 muA. At room temperature, leakage-rate is 1.56 nA/ms. Four-quadrant multiplier (4QM) full-scale operands are 2x(max) = 320 mV(pp) and 2y(max). = 448 mV(pp), yielding a maximum output swing of 0.9 muA(pp). 4QM worst-case nonlinearity is 7.9%.
Resumo:
The interaction of human monocytes or monocyte-derived macrophages and yeast-form Paracoccidioides brasiliensis was studied in vitro. Yeast cells were readily ingested by adherent monocytes or macrophages. Multiplication of P. brasiliensis, measured by growth as colony forming units (cfu) on a supplemented medium with good plating efficiency, was greater in monocyte co-cultures compared to the number of cfu obtained from complete tissue-culture medium (CTCM). Multiplication increased with time in macrophage cocultures, e.g., from two-six-fold in 24 h to nine-fold in 72 h. Microscopic observations indicated that ingested yeast cells multiplied inside macrophages. When monocytes were treated with supernate cytokines (CK) from concanavalin-A-stimulated mononuclear cells, then co-cultured with P. brasiliensis, multiplication was significantly inhibited compared with control monocyte co-cultures. Treatment of macrophages-derived from monocytes by culture in vitro for 3 days-for a further 3 days with CK resulted in maximal inhibition of multiplication over the subsequent 72 h. Similarly, when monocyte-derived macrophages (after culture for 7 days) were treated for 3 days with recombinant human gamma-interferon (IFN; 300 U/ml) or CK they restricted multiplication of P. brasiliensis by 65% and 95%, respectively, compared with control macrophages, Antibody to IFN abrogated the effect of IFN or CK treatment. These findings show that ingested P. brasiliensis can multiply in human monocytes or macrophages and that this multiplication can be restricted by activated monocytes or macrophages.
Resumo:
A CMOS memory-cell for dynamic storage of analog data and suitable for LVLP applications is proposed. Information is memorized as the gate-voltage of input-transistor of a gain-boosting triode-transconductor. The enhanced output-resistance improves accuracy on reading out the sampled currents. Additionally, a four-quadrant multiplication between the input to regulation-amplifier of the transconductor and the stored voltage is provided. Designing complies with a low-voltage 1.2μm N-well CMOS fabrication process. For a 1.3V-supply, CCELL=3.6pF and sampling interval is 0.25μA≤ ISAMPLE ≤ 0.75μA. The specified retention time is 1.28ms and corresponds to a charge-variation of 1% due to junction leakage @75°C. A range of MR simulations confirm circuit performance. Absolute read-out error is below O.40% while the four-quadrant multiplier nonlinearity, at full-scale is 8.2%. Maximum stand-by consumption is 3.6μW/cell.