Impact of Energy Quantization on the Performance of Current-Biased SET Circuits

The current-biased single electron transistor (SET) (CBS) is an integral part of almost all hybrid CMOS SET circuits. In this paper, for the first time, the effects of energy quantization on the performance of CBS-based circuits are studied through analytical modeling and Monte Carlo simulations. It is demonstrated that energy quantization has no impact on the gain of the CBS characteristics, although it changes the output voltage levels and oscillation periodicity. The effects of energy quantization are further studied for two circuits: negative differential resistance (NDR) and neuron cell, which use the CBS. A new model for the conductance of NDR characteristics is also formulated that includes the energy quantization term.

Microbial life and deposits in paper machine circuits

Väitöskirjani käsittele mikrobien ja erilaisten kemikaalien rooleja saostumien ja biofilmien muodostumisessa paperi- ja kartonkikoneilla. "Saostuma" tässä työssä tarkoittaa kiinteän aineen kertymää konepinnoille tai rajapinnoille konekierroissa, jotka on tarkoitettu massasulppujen, lietteiden, vesien tai ilman kuljetukseen. Saostumasta tulee "biofilmi" silloin kun sen oleellinen rakennekomponentti on mikrobisolut tai niiden tuotteet. Väitöstyöni työhypoteesina oli, että i. tietämys saostumien koostumuksesta, sekä ii. niiden rakenteesta, biologisista, fysikaalis-kemiallisista ja teknisistä ominaisuuksista ohjaavat tutkijaa löytämään ympäristöä säästäviä keinoja estää epätoivottujen saostumien muodostus tai purkaa jo muodostuneita saostumia. Selvittääkseni saostumien koostumista ja rakennetta käytin monia erilaisia analytiikan työkaluja, kuten elektronimikroskopiaa, konfokaali-laser mikroskopiaa (CLSM), energiadispersiivistä röntgenanalyysiä (EDX), pyrolyysi kaasukromatografiaa yhdistettynä massaspektrometriaan (Py-GCMS), joninvaihtokromatografiaa, kaasukromatografiaa ja mikrobiologisia analyysejä. Osallistuin aktiivisesti innovatiivisen, valon takaisinsirontaan perustuvan sensorin kehittämistyöhön, käytettäväksi biofilmin kasvun mittaukseen suoraan koneen vesikierroista ja säiliöistä. Työni osoitti, että monet paperinvalmistuksessa käytetyistä kemikaaleista reagoivat keskenään tuottaen orgaanisia tahmakerroksia konekiertojen teräspinnoille. Löysin myös kerrostumia, jotka valomikroskooppisessa tarkastelussa oli tulkittu mikrobeiksi, mutta jotka elektronimikroskopia paljasti alunasta syntyneiksi, alumiinihydroksidiksi joka saostui pH:ssa 6,8 kiertokuitua käyttävän koneen viiravesistä. Monet paperintekijät käyttävät vieläkin alunaa kiinnitysaineena vaikka prosessiolot ovat muuttuneet happamista neutraaleiksi. Sitä pidetään paperitekijän "aspiriinina", mutta väitöstutkimukseni osoitti sen riskit. Löysin myös orgaanisia saostumia, joiden alkuperä oli aineiden, kuten pihkan, saippuoituminen (kalsium saippuat) niin että muodostui tahmankasvua ylläpitävä alusta monilla paperi- ja kartonkikoneilla. Näin solumuodoiltaan Deinococcus geothermalista muistuttavia bakteereita kasvamassa lujasti teräskoepalojen pintaan kiinnittyneinä pesäkkeinä, kun koepaloja upotettiin paperikoneiden vesikiertoihin. Nämä deinokokkimaiset pesäkkeet voivat toimia jalustana, tarttumisalustana muiden mikrobien massoille, joka selittäisi miksi saostumat yleisesti sisältävät deinokokkeja pienenä, muttei koskaan pääasiallisena rakenneosana. Kun paperikoneiden käyttämien vesien (raakavedet, lämminvesi, biologisesti puhdistettu jätevesi) laatua tutkitaan, mittausmenetelmällä on suuri merkitys. Koepalan upotusmenetelmällä todettu biofilmikasvu ja viljelmenetelmällä mitattu bakteerisaastuneisuus korreloivat toisiinsa huonosti etenkin silloin kun likaantumisessa oli mukana rihmamaiseti kasvavia bakteereja. Huoli ympäristöstä on pakottanut paperi- ja kartonkikoneiden vesikiertojen sulkemiseen. Vesien kierrätys ja prosessivesien uudelleenkäyttö nostavat prosessilämpötilaa ja lisäävät koneella kiertävien kolloidisten ja liuenneiden aineiden määriä. Tutkin kiertovesien pitoisuuksia kolmessa eriasteisesti suljetussa tehtaassa, joiden päästöt olivat 0 m3, 0,5 m3 ja 4 m3 jätevettä tuotetonnia kohden, perustuen puhdistetun jäteveden uudelleen käyttöön. Nollapäästöisellä tehtaalla kiertovesiin kertyi paljon orgaanisesti sidottua hiiltä (> 10 g L-1), etenkin haihtuvina happoina (maito-, etikka-, propioni- ja voi-). Myös sulfaatteja, klorideja, natriumia ja kalsiumia kertyi paljon, > 1 g L-1 kutakin. Pääosa (>40%) kaikista bakteereista oli 16S rRNA geenisekvenssianalyysien tulosten perusteella sukua, joskin etäistä (< 96%) ainoastaan Enterococcus cecorum bakteerille. 4 m3 päästävältä tehtaalta löytyi lisäksi Bacillus thermoamylovorans ja Bacillus coagulans. Tehtaiden saostumat sisälsivät arkkeja suurina pitoisuuksina, ≥ 108 g-1, mutta tunnistukseen riittävää sekvenssisamanlaisuutta löytyi vain yhteen arkkisukuun, Methanothrix. Tutkimustulokset osoittivat että tehtaan vesikiertojen sulkeminen vähensi rajusti mikrobiston monimuotoisuutta, muttei estänyt liuenneen aineen ja kiintoaineen mineralisoitumista.

A new family of low-power CT/SUP 2/L circuits

A new family of low-power logic circuits, employing a multiemitter transistor input circuit and a modified complementary p-n-p n-p-n output stage, having almost the same performance as standard TTL circuits and suitable for IC use, is reported in this correspondence.

Multi-Tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients

A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies in addition to DC. Classification or Cur is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. This testing method requires no design for test hardware as might be added to the circuit fly some other methods. The proposed method is illustrated for a benchmark elliptic filter. It is shown to uncover several parametric faults causing deviations as small as 5% from the nominal values.

Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits

In this paper, the effects of energy quantization on different single-electron transistor (SET) circuits (logic inverter, current-biased circuits, and hybrid MOS-SET circuits) are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantizationmainly increases the Coulomb blockade area and Coulomb blockade oscillation periodicity, and thus, affects the SET circuit performance. A new model for the noise margin of the SET inverter is proposed, which includes the energy quantization effects. Using the noise margin as a metric, the robustness of the SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as ``quantization threshold'') that an SET inverter can withstand before its noise margin falls below a specified tolerance level. The effects of energy quantization are further studiedfor the current-biased negative differential resistance (NDR) circuitand hybrid SETMOS circuit. A new model for the conductance of NDR characteristics is also formulated that explains the energy quantization effects.

On the performance analysis of a class of neuron circuits

A new performance metric, Peak-Error Ratio (PER) has been presented to benchmark the performance of a class of neuron circuits to realize neuron activation function (NAF) and its derivative (DNAF). Neuron circuits, biased in subthreshold region, based on the asymmetric cross-coupled differential pair configuration and conventional configuration of applying small external offset voltage at the input have been compared on the basis of PER. It is shown that the technique of using transistor asymmetry in a cross-coupled differential pair performs on-par with that of applying external offset voltage. The neuron circuits have been experimentally prototyped and characterized as a proof of concept on the 1.5 mu m AMI technology.

On the performance analysis of a class of neuron circuits

A new performance metric, Peak-Error Ratio (PER) has been presented to benchmark the performance of a class of neuron circuits to realize neuron activation function (NAF) and its derivative (DNAF). Neuron circuits, biased in subthreshold region, based on the asymmetric cross-coupled differential pair configuration and conventional configuration of applying small external offset voltage at the input have been compared on the basis of PER. It is shown that the technique of using transistor asymmetry in a cross-coupled differential pair performs on-par with that of applying external offset voltage. The neuron circuits have been experimentally prototyped and characterized as a proof of concept on the 1.5 mu m AMI technology.

Language and the Circuits of Power in a Merging Multinational Corporation

We argue in this paper that corporate language policies have significant power implications that are easily overlooked. By drawing on previous work on power in organizations (Clegg, 1989), we examine the complex power implications of language policy decisions by looking at three levels of analysis: episodic social interaction, identity/subjectivity construction, and reconstruction of structures of domination. In our empirical analysis, we focus on the power implications of the choice of Swedish as the corporate language in the case of the recent banking sector merger between the Finnish Merita and the Swedish Nordbanken. Our findings show how language skills become empowering or disempowering resources in organizational communication, how these skills are associated with professional competence, and how this leads to the creation of new social networks. The case also illustrates how language skills are an essential element in the construction of international confrontation, lead to a construction of superiority and inferiority, and also reproduce post-colonial identities in the merging bank. Finally, we also point out how such policies ultimately lead to the reification of post-colonial and neo-colonial structures of domination in multinational corporations.

Language and the circuits of power in a merging multinational corporation

We argue in this paper that corporate language policies have significant power implications that are easily overlooked. By drawing on previous work on power in organizations (Clegg, 1989), we examine the complex power implications of language policy decisions by looking at three levels of analysis: episodic social interaction, identity/subjectivity construction, and reconstruction of structures of domination. In our empirical analysis, we focus on the power implications of the choice of Swedish as the corporate language in the case of the recent banking sector merger between the Finnish Merita and the Swedish Nordbanken. Our findings show how language skills become empowering or disempowering resources in organizational communication, how these skills are associated with professional competence, and how this leads to the creation of new social networks. The case also illustrates how language skills are an essential element in the construction of international confrontation, lead to a construction of superiority and inferiority, and also reproduce post-colonial identities in the merging bank. Finally, we also point out how such policies ultimately lead to the reification of post-colonial and neo-colonial structures of domination in multinational corporations.

Low Power continuous time common mode sensing for common mode feedback circuits

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 mu m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits.

Al/SiC carriers for microwave integrated circuits by a new technique of pressureless infiltration

Materials with high thermal conductivity and thermal expansion coefficient matching with that of Si or GaAs are being used for packaging high density microcircuits due to their ability of faster heat dissipation. Al/SiC is gaining wide acceptance as electronic packaging material due to the fact that its thermal expansion coefficient can be tailored to match with that of Si or GaAs by varying the Al:SiC ratio while maintaining the thermal conductivity more or less the same. In the present work, Al/SiC microwave integrated circuit (MIC) carriers have been fabricated by pressureless infiltration of Al-alloy into porous SiC preforms in air. This new technique provides a cheaper alternative to pressure infiltration or pressureless infiltration in nitrogen in producing Al/SiC composites for electronic packaging applications. Al-alloy/65vol% SiC composite exhibited a coefficient of thermal expansion of 7 x 10(-6) K-1 (25 degrees C-100 degrees C) and a thermal conductivity of 147 Wm(-1) K-1 at 30 degrees C. The hysteresis observed in thermal expansion coefficient of the composite in the temperature range 100 degrees C-400 degrees C has been attributed to the presence of thermal residual stresses in the composite. Thermal diffusivity of the composite measured over the temperature range from 30 degrees C to 400 degrees C showed a 55% decrease in thermal diffusivity with temperature. Such a large decrease in thermal diffusivity with temperature could be due to the presence of micropores, microcracks, and decohesion of the Al/SiC interfaces in the microstructure (all formed during cooling from the processing temperature). The carrier showed satisfactory performance after integrating it into a MIC.

Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor-single electron transistor integrated circuits

For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique

The increasing variability in device leakage has made the design of keepers for wide OR structures a challenging task. The conventional feedback keepers (CONV) can no longer improve the performance of wide dynamic gates for the future technologies. In this paper, we propose an adaptive keeper technique called rate sensing keeper (RSK) that enables faster switching and tracks the variation across different process corners. It can switch upto 1.9x faster (for 20 legs) than CONV and can scale upto 32 legs as against 20 legs for CONV in a 130-nm 1.2-V process. The delay tracking is within 8% across the different process corners. We demonstrate the circuit operation of RSK using a 32 x 8 register file implemented in an industrial 130-nm 1.2-V CMOS process. The performance of individual dynamic logic gates are also evaluated on chip for various keeper techniques. We show that the RSK technique gives superior performance compared to the other alternatives such as Conditional Keeper (CKP) and current mirror-based keeper (LCR).

In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits

An in-situ power monitoring technique for Dynamic Voltage and Threshold scaling (DVTS) systems is proposed which measures total power consumed by load circuit using sleep transistor acting as power sensor. Design details of power monitor are examined using simulation framework in UMC 90nm CMOS process. Experimental results of test chip fabricated in AMS 0.35µm CMOS process are presented. The test chip has variable activity between 0.05 and 0.5 and has PMOS VTH control through nWell contact. Maximum resolution obtained from power monitor is 0.25mV. Overhead of power monitor in terms of its power consumption is 0.244 mW (2.2% of total power of load circuit). Lastly, power monitor is used to demonstrate closed loop DVTS system. DVTS algorithm shows 46.3% power savings using in-situ power monitor.

Circuits on cylinders

We consider the computational power of constant width polynomial size cylindrical circuits and non deterministic branching programs. We show that every function computed by a Pi(2) o MOD o AC(0) circuit can also be computed by a constant width polynomial size cylindrical nondeterministic branching program (or cylindrical circuit) and that every function computed by a constant width polynomial size cylindrical circuit belongs to ACC(0).