Selected problems of minimization of variable-valued logic formulas /

"UIUCDCS-R-75-726"

Toward computer-aided induction : a brief review of currently implemented AQVAL programs /

"UILU-ENG 77 1726."

The methodology of knowledge layers for inducing descriptions of sequentially ordered events /

"UILU-ENG 80 1719"--Cover.

Synthesis Methods of Multiple-valued Structures of Language Systems

The basic construction concepts of many-valued intellectual systems, which are adequate to primal problems of person activity and using hybrid tools with many-valued of coding are considered. The many-valued intellectual systems being two-place, but simulating neuron processes of space toting which are different on a level of actions, inertial and threshold of properties of neurons diaphragms, and also modification of frequency of following of the transmitted messages are created. All enumerated properties and functions in point of fact are essential not only are discrete on time, but also many-valued.

Multiple-Valued Structures of Intellectual Systems

The basic construction concepts of many-valued intellectual systems, which are adequate to primal problems of person activity and using hybrid tools with many-valued intellectual systems being two-place, but simulating neuron processes of space toting which are different on a level of actions, inertial and threshold of properties of neuron diaphragms, and also frequency modification of the following transmitted messages are created. All enumerated properties and functions in point of fact are essential not only are discrete on time, but also many-valued.

Of madness and many-valuedness: an investigation into Suszko's Thesis

Suszko’s Thesis is a philosophical claim regarding the nature of many-valuedness. It was formulated by the Polish logician Roman Suszko during the middle 70s and states the existence of “only but two truth values”. The thesis is a reaction against the notion of many-valuedness conceived by Jan Łukasiewicz. Reputed as one of the modern founders of many-valued logics, Łukasiewicz considered a third undetermined value in addition to the traditional Fregean values of Truth and Falsehood. For Łukasiewicz, his third value could be seen as a step beyond the Aristotelian dichotomy of Being and non-Being. According to Suszko, Łukasiewicz’s ideas rested on a confusion between algebraic values (what sentences describe/denote) and logical values (truth and falsity). Thus, Łukasiewicz’s third undetermined value is no more than an algebraic value, a possible denotation for a sentence, but not a genuine logical value. Suszko’s Thesis is endorsed by a formal result baptized as Suszko’s Reduction, a theorem that states every Tarskian logic may be characterized by a two-valued semantics. The present study is intended as a thorough investigation of Suszko’s thesis and its implications. The first part is devoted to the historical roots of many-valuedness and introduce Suszko’s main motivations in formulating the double character of truth-values by drawing the distinction in between algebraic and logical values. The second part explores Suszko’s Reduction and presents the developments achieved from it; the properties of two-valued semantics in comparison to many-valued semantics are also explored and discussed. Last but not least, the third part investigates the notion of logical values in the context of non-Tarskian notions of entailment; the meaning of Suszko’s thesis within such frameworks is also discussed. Moreover, the philosophical foundations for non-Tarskian notions of entailment are explored in the light of recent debates concerning logical pluralism.

Reed-Muller Canonical Forms in Multivalued Logic

Canonical forms for m-valued functions referred to as m-Reed-Muller canonical (m-RMC) forms that are a generalization of RMC forms of two-valued functions are proposed. m-RMC forms are based on the operations ?m (addition mod m) and .m (multiplication mod m) and do not, as in the cases of the generalizations proposed in the literature, require an m-valued function for m not a power of a prime, to be expressed by a canonical form for M-valued functions, where M > m is a power of a prime. Methods of obtaining the m-RMC forms from the truth vector or the sum of products representation of an m-valued function are discussed. Using a generalization of the Boolean difference to m-valued logic, series expansions for m-valued functions are derived.

Compact voltage-mode multi-valued literal gate using nanoscale ballistic MOSFETs

A CMOS voltage-mode multi-valued literal gate is presented. The ballistic electron transport characteristic of nanoscale MOSFETs is smartly used to compactly achieve universal radix-4 literal operations. The proposed literal gates have small numbers of transistors and low power dissipations, which makes them promising for future nanoscale multi-valued circuits. The gates are simulated by HSPICE.

Qualitative Modelling of Linear Networks in ECAD Applications

Lee M.H., Qualitative Modelling of Linear Networks in ECAD Applications, Expert Update, Vol. 3, Num. 2, pp23-32, BCS SGES, Summer 2000. Qualitative modeling of linear networks in ecad applications (1999) by M Lee Venue: Pages 146?152 of: Proceedings 13th international workshop on qualitative reasoning, QR ?99

Logics for belief functions on MV-algebras

In this paper we present a generalization of belief functions over fuzzy events. In particular we focus on belief functions defined in the algebraic framework of finite MV-algebras of fuzzy sets. We introduce a fuzzy modal logic to formalize reasoning with belief functions on many-valued events. We prove, among other results, that several different notions of belief functions can be characterized in a quite uniform way, just by slightly modifying the complete axiomatization of one of the modal logics involved in the definition of our formalism. © 2012 Elsevier Inc. All rights reserved.

The Finite Embeddability Property for some noncommutative knotted varieties of RL and DRL.

Residuated lattices, although originally considered in the realm of algebra providing a general setting for studying ideals in ring theory, were later shown to form algebraic models for substructural logics. The latter are non-classical logics that include intuitionistic, relevance, many-valued, and linear logic, among others. Most of the important examples of substructural logics are obtained by adding structural rules to the basic logical calculus

Applications of Nonclassical Logic Methods for Purposes of Knowledge Discovery and Data Mining

* The work is partially supported by Grant no. NIP917 of the Ministry of Science and Education – Republic of Bulgaria.

Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor-single electron transistor integrated circuits

For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Compact non-binary fast adders using single-electron devices

This paper proposes compact adders that are based on non-binary redundant number systems and single-electron (SE) devices. The adders use the number of single electrons to represent discrete multiple-valued logic state and manipulate single electrons to perform arithmetic operations. These adders have fast speed and are referred as fast adders. We develop a family of SE transfer circuits based on MOSFET-based SE turnstile. The fast adder circuit can be easily designed by directly mapping the graphical counter tree diagram (CTD) representation of the addition algorithm to SE devices and circuits. We propose two design approaches to implement fast adders using SE transfer circuits the threshold approach and the periodic approach. The periodic approach uses the voltage-controlled single-electron transfer characteristics to efficiently achieve periodic arithmetic functions. We use HSPICE simulator to verify fast adders operations. The speeds of the proposed adders are fast. The numbers of transistors of the adders are much smaller than conventional approaches. The power dissipations are much lower than CMOS and multiple-valued current-mode fast adders. (C) 2009 Elsevier Ltd. All rights reserved.

Performing Fast Addition and Multiplication by Transferring Single Electrons

This paper proposes novel fast addition and multiplication circuits that are based on non-binary redundant number systems and single electron (SE) devices. The circuits consist of MOSFET-based single-electron (SE) turnstiles. We use the number of electrons to represent discrete multiple-valued logic states and we finish arithmetic operations by controlling the number of electrons transferred. We construct a compact PD2,3 adder and a 12x12bit multiplier using the PD2,3 adder. The speed of the adder can be as high as 600MHz with 400nW power dissipation. The speed of the adder is regardless of its operand length. The proposed circuits have much smaller transistors than conventional circuits.