Is the irritable bladder associated with anterior compartment relaxation? A critical look at the 'integral theory of pelvic floor dysfunction'

The 'integral theory of pelvic floor dysfunction', first proposed by Petros and Ulmsten in 1990, claims that anterior vaginal wall relaxation is associated with symptoms of urgency, frequency, nocturia and urge incontinence. A retrospective study was designed to test this hypothesis. Imaging data and urodynamic reports from 272 women suffering from symptoms of lower urinary tract dysfunction were evaluated. Opening of the retrovesical angle, bladder neck descent, urethral rotation and descent of a cystocele during Valsalva were used to quantify anterior vaginal wall laxity None of the tested parameters were associated with symptoms and signs of detrusor overactivity. On the contrary, patients with higher grades of urethral and bladder descent were less likely to suffer from nocturia and urge incontinence and were less likely to leave sensory urgency and detrusor instability diagnosed on urodynamic testing. The findings of this study therefore do not support this hypothesis of the 'integral theory'.

What does the field of International Relations look like in South America?

Abstract This article provides a comprehensive picture of IR in South America by applying content analysis to 7,857 articles published in 35 journals from six South American countries from 2006 to 2014 in order to discover what the predominant theories, methods and research areas in this field are, how scholars tend to combine them in their research designs, and what the profiles of regional journals are, regarding their epistemological, methodological and subject preferences. The findings reveal a predominantly Positivist and largely Qualitative discipline, resembling North American and European IR.

New Features to Look at Natural Phenomena

Proceeding of the 3rd International Conference on Fractional Systems and Signals, at Ghent, Belgium

La lista de Angel piedras. Memória de la guerra civil y subalternidad

Ángel Piedras naciô en Nava dei Rey província de Valladolid (Espana), en 1910. Hijo de una família de jomaleros, tambiên él ti"abajó en ei campo hasta los veintiséis afios. Fue detenido y encarcelado en los dias de Ia terrible represión que sucedíó ai alzamíento franquista. Trás 101 dias de condena a muerte, su pena fue conmutada por Ia de cárcel. Salíó indultado en 1944. Ángel Piedras era hermano de mi abuelo, fusílado en Cáceres en enero de 1938. Su testímonio tiene que ver decisivamente con mi ínterés y mi dedicación a Ia historia. Este pequefío ensayo, primera piedra de un trabajo más amplio, es ante todo una prueba de mi admíración y mi agradecimiento hacia él. Guando Ángel Piedras muere en 1997, deja en casa de su hija Petra, persona clave en nuestro trabajo, una caja con materíales muy diversos, entre los que se encontraban vários cuademos, varias listas de represaliados y diversos manuscritos más, principalmente con ripios y poemas memorizados y transcritos por él.

A look into the cross-section of industry stock returns

A Work Project, presented as part of the requirements for the Award of a Masters Degree in Finance from the NOVA – School of Business and Economics

A closer look at brazilwood and its lake pigments

Dissertação para obtenção do Grau de Mestre em Mestrado em Conservação e Restauro, especialização em Ciências da Conservação

Microfluidics: a new look at cell migration analysis

This thesis explores the development and employment of microfluidic devices as a tool for studying the effect of the surrounding environment on embryonic stem cells during the migration phenomena. Different single-cell microchips were designed and manufactured to study mouse embryonic fibroblasts (MEFs) migration towards an environmental variation (increase of serum concentration in the culture medium) that was expected to function as a motility stimuli. Considering the experimental, cells were injected into the microchips chambers and individually isolated by dedicated cell traps with view to a single-cell analysis. Once fribroblasts were attached to the surface, culture medium with an increased serum level was subsequently injected in an adjacent chamber to promote the formation of a serum concentration gradient. The gradient established between the chambers could be sensed by the fibroblasts and thus triggered the cells mobilization towards and in the direction of the richer serum medium. Additionally, the experiment allowed the observation of MEFs’ structural reorganization when migrating through micro-tunnels containing widths below the cell size, suggesting a cytoskeleton rearrangement on account of the nutritional stimulus introduced. Furthermore, results indicate that fibronectin promotes MEFs adhesion to the substrate and that MEFs migration is characterized as haptotactic.

Deflation and monetary policy: A look into Japan and the Euro Area

With more than two decades of weak economic performance since the bubble burst in the ‘90s, the Japanese deflationary scenario has become the economic fate every developed economy fears to become. As the euro area continues to experience sustained low inflation, studying the Japanese monetary policy may shed light on how to prevent persistent deflation. Using an SVAR methodology to understand the monetary transmission mechanism, we find some evidence that the euro area may possess characteristics that would eventually lead to a deflationary scenario. The extent of whether it would suffer the same Japanese fate would depend on how macroeconomic policies are timely coordinated as a response to its liquidity problem and increasing public debt across member states.

Aceleración de Algoritmos en Procesadores Multicore, GPGPU y FPGA. Algorithm Acceleration with Multicore, GPGPU and FPGA Processors.

El avance en la potencia de cómputo en nuestros días viene dado por la paralelización del procesamiento, dadas las características que disponen las nuevas arquitecturas de hardware. Utilizar convenientemente este hardware impacta en la aceleración de los algoritmos en ejecución (programas). Sin embargo, convertir de forma adecuada el algoritmo en su forma paralela es complejo, y a su vez, esta forma, es específica para cada tipo de hardware paralelo. En la actualidad los procesadores de uso general más comunes son los multicore, procesadores paralelos, también denominados Symmetric Multi-Processors (SMP). Hoy en día es difícil hallar un procesador para computadoras de escritorio que no tengan algún tipo de paralelismo del caracterizado por los SMP, siendo la tendencia de desarrollo, que cada día nos encontremos con procesadores con mayor numero de cores disponibles. Por otro lado, los dispositivos de procesamiento de video (Graphics Processor Units - GPU), a su vez, han ido desarrollando su potencia de cómputo por medio de disponer de múltiples unidades de procesamiento dentro de su composición electrónica, a tal punto que en la actualidad no es difícil encontrar placas de GPU con capacidad de 200 a 400 hilos de procesamiento paralelo. Estos procesadores son muy veloces y específicos para la tarea que fueron desarrollados, principalmente el procesamiento de video. Sin embargo, como este tipo de procesadores tiene muchos puntos en común con el procesamiento científico, estos dispositivos han ido reorientándose con el nombre de General Processing Graphics Processor Unit (GPGPU). A diferencia de los procesadores SMP señalados anteriormente, las GPGPU no son de propósito general y tienen sus complicaciones para uso general debido al límite en la cantidad de memoria que cada placa puede disponer y al tipo de procesamiento paralelo que debe realizar para poder ser productiva su utilización. Los dispositivos de lógica programable, FPGA, son dispositivos capaces de realizar grandes cantidades de operaciones en paralelo, por lo que pueden ser usados para la implementación de algoritmos específicos, aprovechando el paralelismo que estas ofrecen. Su inconveniente viene derivado de la complejidad para la programación y el testing del algoritmo instanciado en el dispositivo. Ante esta diversidad de procesadores paralelos, el objetivo de nuestro trabajo está enfocado en analizar las características especificas que cada uno de estos tienen, y su impacto en la estructura de los algoritmos para que su utilización pueda obtener rendimientos de procesamiento acordes al número de recursos utilizados y combinarlos de forma tal que su complementación sea benéfica. Específicamente, partiendo desde las características del hardware, determinar las propiedades que el algoritmo paralelo debe tener para poder ser acelerado. Las características de los algoritmos paralelos determinará a su vez cuál de estos nuevos tipos de hardware son los mas adecuados para su instanciación. En particular serán tenidos en cuenta el nivel de dependencia de datos, la necesidad de realizar sincronizaciones durante el procesamiento paralelo, el tamaño de datos a procesar y la complejidad de la programación paralela en cada tipo de hardware. Today´s advances in high-performance computing are driven by parallel processing capabilities of available hardware architectures. These architectures enable the acceleration of algorithms when thes ealgorithms are properly parallelized and exploit the specific processing power of the underneath architecture. Most current processors are targeted for general pruposes and integrate several processor cores on a single chip, resulting in what is known as a Symmetric Multiprocessing (SMP) unit. Nowadays even desktop computers make use of multicore processors. Meanwhile, the industry trend is to increase the number of integrated rocessor cores as technology matures. On the other hand, Graphics Processor Units (GPU), originally designed to handle only video processing, have emerged as interesting alternatives to implement algorithm acceleration. Current available GPUs are able to implement from 200 to 400 threads for parallel processing. Scientific computing can be implemented in these hardware thanks to the programability of new GPUs that have been denoted as General Processing Graphics Processor Units (GPGPU).However, GPGPU offer little memory with respect to that available for general-prupose processors; thus, the implementation of algorithms need to be addressed carefully. Finally, Field Programmable Gate Arrays (FPGA) are programmable devices which can implement hardware logic with low latency, high parallelism and deep pipelines. Thes devices can be used to implement specific algorithms that need to run at very high speeds. However, their programmability is harder that software approaches and debugging is typically time-consuming. In this context where several alternatives for speeding up algorithms are available, our work aims at determining the main features of thes architectures and developing the required know-how to accelerate algorithm execution on them. We look at identifying those algorithms that may fit better on a given architecture as well as compleme

Genera mammalium, por Angel Cabrera. Monotremata, Marsupialia (con 19 láminas en color)

(1919)

Fast and furious: a look at the death of animals on the highway MS-080, Southwestern Brazil

Several factors, such as hunting and the pet trade, are responsible for the worldwide decline of wildlife populations. In addition, fatal collisions with vehicles on highways have also taken one of the largest tolls. This study aimed to quantify the richness and abundance of vertebrate roadkill along highway MS-080 in Mato Grosso do Sul, Central-West Brazil. We compare the amount of roadkill to the distance between cities, moon phases and the flow of vehicles on the highway. Samples were collected weekly between March and September 2011, totaling 257 individuals, belonging to 32 families and 52 species, resulting in an index of 0.13 individuals hit/km. Birds were the most frequently hit taxa, followed by mammals. The most affected species was Cariama cristata (Cariamidae), followed by Cerdocyon thous (Canidae). The sections of highway closest to cities had the highest number of individual animals killed. Our observations indicate that the density of the vegetation next to the highway positively influences the amount of roadkill.

A Descriptive and analytic look at Marx's own explanations of the falling rate of profit (second version)

This paper examines, both descriptively and analytically, Marx's arguments for the falling rate of profit from the Hodgskin section of Theories of Surplus Value, The General Law section of the recently published Volume 33 of the Collected Works and Chapter 3 of Volume III of Capital. The conclusions are as follows: First, Marx realised that his main attempt to give an intrinsic explanation of the falling rate of profit, which occurred in the General Law section, had failed; but he still hoped that he would be able to demonstrate it in the future. Second, the Hodgskin and General Law sections contain a number of subsidiary explanations, mostly related to resource scarcity, some of which are correct. Third, Part III of volume III does not contain a demonstration of the falling rate of profit, but a description of the role of the falling rate of profit in capitalist development. Forth, it also contains suppressed references to resource scarcity. And finally, in Chapter 3 of Volume III, Marx says that it is resource scarcity that causes the fall in the rate of profit described in Part III of the same volume. The key to all these conclusions in the careful analysis of the General Law section.