Concatenated all-optical loop mirror switches

Synthesis of a sharp switching characteristic is experimentally demonstrated by concatenation of nonlinear optical loop mirrors. A novel configuration has been used which results in three terminal operation of the device. This device can be used as a logic gate and for pulse shaping to produce square pulses. © 1993 Taylor and Francis Ltd.

METAMATERIAL DEVICE AND USES THEREOF

The present invention relates to a logic gate, comprising a metamaterial surface enhanced Raman scattering (MetaSERS) sensor, comprising (a) alphabetical metamaterials in the form of split ring resonators operating in the wavelength range of from 560 to 2200 nm; and (b) a guanine (G) and thymine (T)-rich oligonucleotide that can, upon presence of potassium cations (K+), fold into a G-quadruplex structure, and in presence of Hg2+, form a T-Hg2+-T hairpin complex that inhibits or disrupts the G-quadruplex structure formed in presence of K+, as well as methods of operating and using such a logic gate.

Electrical characterization of electronic circuits produced by inkjet printing

Dissertação de Mestrado, Engenharia Electrónica e Telecomunicações, Faculdade de Ciências e Tecnologia, Universidade do Algarve, 2014

Species differential regulation of COX2 can be described by an NFκB-dependent logic AND gate

Cyclooxygenase 2 (COX2), a key regulatory enzyme of the prostaglandin/eicosanoid pathway, is an important target for anti-inflammatory therapy. It is highly induced by pro-inflammatory cytokines in a Nuclear factor kappa B (NFκB)-dependent manner. However, the mechanisms determining the amplitude and dynamics of this important pro-inflammatory event are poorly understood. Furthermore, there is significant difference between human and mouse COX2 expression in response to the inflammatory stimulus tumor necrosis factor alpha (TNFα). Here, we report the presence of a molecular logic AND gate composed of two NFκB response elements (NREs) which controls the expression of human COX2 in a switch-like manner. Combining quantitative kinetic modeling and thermostatistical analysis followed by experimental validation in iterative cycles, we show that the human COX2 expression machinery regulated by NFκB displays features of a logic AND gate. We propose that this provides a digital, noise-filtering mechanism for a tighter control of expression in response to TNFα, such that a threshold level of NFκB activation is required before the promoter becomes active and initiates transcription. This NFκB-regulated AND gate is absent in the mouse COX2 promoter, most likely contributing to its differential graded response in promoter activity and protein expression to TNFα. Our data suggest that the NFκB-regulated AND gate acts as a novel mechanism for controlling the expression of human COX2 to TNFα, and its absence in the mouse COX2 provides the foundation for further studies on understanding species-specific differential gene regulation.

Quantum controlled-NOT gate with 'hot' trapped ions

We present a novel method of performing quantum logic gates in trapped ion quantum computers which does not require the ions to be cooled down to the ground state of their vibrational modes, thereby avoiding one of the principal experimental difficulties encountered in realizing this technology. Our scheme employs adiabatic passages and a phase shift conditional on the phonon number state.

Nondeterministic gates for photonic single-rail quantum logic

We discuss techniques for producing, manipulating, and measuring qubits encoded optically as vacuum- and single-photon states. We show that a universal set of nondeterministic gates can be constructed using linear optics and photon counting. We investigate the efficacy of a test gate given realistic detector efficiencies.

System-on-chip field-programmable gate array design for onboard real-time hyperspectral unmixing

Hyperspectral instruments have been incorporated in satellite missions, providing large amounts of data of high spectral resolution of the Earth surface. This data can be used in remote sensing applications that often require a real-time or near-real-time response. To avoid delays between hyperspectral image acquisition and its interpretation, the last usually done on a ground station, onboard systems have emerged to process data, reducing the volume of information to transfer from the satellite to the ground station. For this purpose, compact reconfigurable hardware modules, such as field-programmable gate arrays (FPGAs), are widely used. This paper proposes an FPGA-based architecture for hyperspectral unmixing. This method based on the vertex component analysis (VCA) and it works without a dimensionality reduction preprocessing step. The architecture has been designed for a low-cost Xilinx Zynq board with a Zynq-7020 system-on-chip FPGA-based on the Artix-7 FPGA programmable logic and tested using real hyperspectral data. Experimental results indicate that the proposed implementation can achieve real-time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high-performance, low-cost embedded systems, opening perspectives for onboard hyperspectral image processing.

Power supply noise and logic error probability

Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing two effects: a degradation of performances mainly impacting gate delays anda noisy contamination of the quiescent levels of the logic that drives the node. Both effects are presented together, in thispaper, showing than both are a cause of errors in modern and future digital circuits. The paper groups both error mechanismsand shows how the global error rate is related with the voltage deviation and the period of the clock of the digital system.

Field-Programmable Gate Array Card for Readout and Control of Cryoelectronics

The main goal of the present Master’s Thesis project was to create a field-programmable gate array (FPGA) based system for the control of single-electron transistors or other cryoelectronic devices. The FPGA and similar technologies are studied in the present work. The fixed and programmable logic are compared with each other. The main features and limitations of the hardware used in the project are investigated. The hardware and software connections of the device to the computer are shown in detail. The software development techniques for FPGA-based design are described. The steps of design for programmable logic are considered. Furthermore, the results of filters implemented in the software are illustrated.

Four-level systems and a universal quantum gate

We discuss the possibility of implementing a universal quantum XOR gate by using two coupled quantum dots subject to external magnetic fields that are parallel and slightly different. We consider this system in two different field configurations. In the first case, parallel external fields with the intensity difference at each spin being proportional to the time-dependent interaction between the spins. A general exact solution describing this system is presented and analyzed to adjust field parameters. Then we consider parallel fields with intensity difference at each spin being constant and the interaction between the spins switching on and off adiabatically. In both cases we adjust characteristics of the external fields (their intensities and duration) in order to have the parallel pulse adequate for constructing the XOR gate. In order to provide a complete theoretical description of all the cases, we derive relations between the spin interaction, the inter-dot distance, and the external field. (C) 2008 WILEYNCH Verlag GmbH & Co. KGaA. Weinheim.

Programmable logic design of a compact Genetic Algorithm for phasor estimation in real-time

The main objective of this work is to present an efficient method for phasor estimation based on a compact Genetic Algorithm (cGA) implemented in Field Programmable Gate Array (FPGA). To validate the proposed method, an Electrical Power System (EPS) simulated by the Alternative Transients Program (ATP) provides data to be used by the cGA. This data is as close as possible to the actual data provided by the EPS. Real life situations such as islanding, sudden load increase and permanent faults were considered. The implementation aims to take advantage of the inherent parallelism in Genetic Algorithms in a compact and optimized way, making them an attractive option for practical applications in real-time estimations concerning Phasor Measurement Units (PMUs).

Low-power vertical cavity NAND gate

The study of the Vertical-Cavity Semiconductor Optical Amplifiers (VCSOAs) for optical signal processing applications is increasing his interest. Due to their particular structure, the VCSOAs present some advantages when compared to their edge-emitting counterparts including low manufacturing costs, high coupling efficiency to optical fibers and the ease to fabricate 2-D arrays of this kind of devices. As a consequence, all-optical logic gates based on VCSOAs may be very promising devices for their use in optical computing and optical switching in communications. Moreover, since all the boolean logic functions can be implemented by combining NAND logic gates, the development of a Vertical-Cavity NAND gate would be of particular interest. In this paper, the characteristics of the dispersive optical bistability appearing on a VCSOA operated in reflection are studied. A progressive increment of the number of layers compounding the top Distributed Bragg Reflector (DBR) of the VCSOA results on a change on the shape of the appearing bistability from an S-shape to a clockwise bistable loop. This resulting clockwise bistability has high on-off contrast ratio and input power requirements one order of magnitude lower than those needed for edge-emitting devices. Based on these results, an all-optical vertical-cavity NAND gate with high on-off contrast ratio and an input power for operation of only 10|i\V will be reported in this paper.

A self-timed multipurpose delay sensor for field programmable gate arrays (FPGAs)

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor’s measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration.

Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis

Conventional dual-rail precharge logic suffers from difficult implementations of dual-rail structure for obtaining strict compensation between the counterpart rails. As a light-weight and high-speed dual-rail style, balanced cell-based dual-rail logic (BCDL) uses synchronised compound gates with global precharge signal to provide high resistance against differential power or electromagnetic analyses. BCDL can be realised from generic field programmable gate array (FPGA) design flows with constraints. However, routings still exist as concerns because of the deficient flexibility on routing control, which unfavourably results in bias between complementary nets in security-sensitive parts. In this article, based on a routing repair technique, novel verifications towards routing effect are presented. An 8 bit simplified advanced encryption processing (AES)-co-processor is executed that is constructed on block random access memory (RAM)-based BCDL in Xilinx Virtex-5 FPGAs. Since imbalanced routing are major defects in BCDL, the authors can rule out other influences and fairly quantify the security variants. A series of asymptotic correlation electromagnetic (EM) analyses are launched towards a group of circuits with consecutive routing schemes to be able to verify routing impact on side channel analyses. After repairing the non-identical routings, Mutual information analyses are executed to further validate the concrete security increase obtained from identical routing pairs in BCDL.

Program manual, NOR network transduction by generalized gate merging and substitution : (reference manual of NOR network transduction programs NETTRA-G3 and NETTRA-G4) /

Includes bibliographical references.