Analysis of the gate capacitance measurement technique and its application for the evaluation of hot-carrier degradation in submicrometer MOSFETs

The use of gate-to-drain capacitance (C-gd) measurement as a tool to characterize hot-carrier-induced charge centers in submicron n- and p-MOSFET's has been reviewed and demonstrated. By analyzing the change in C-gd measured at room and cryogenic temperature before and after high gate-to-drain transverse field (high field) and maximum substrate current (I-bmax) stress, it is concluded that the degradation was found to be mostly due to trapping of majority carriers and generation of interface states. These interface states were found to be acceptor states at top half of band gap for n-MOSFETs and donor states at bottom half of band gap for p-MOSFETs. In general, hot electrons are more likely to be trapped in gate oxide as compared to hot holes while the presence of hot holes generates more interface states. Also, we have demonstrated a new method for extracting the spatial distribution of oxide trapped charge, Q(ot), through gate-to-substrate capacitance (C-gb) measurement. This method is simple to implement and does not require additional information from simulation or detailed knowledge of the device's structure. (C) 2001 Elsevier Science Ltd. All rights reserved.

A multiplying-by-two CMOS amplifier for high-speed ADCs based on parametric amplification

15th International Conference on Mixed Design of Integrated Circuits and Systems, pp. 177 – 180, Poznan, Polónia

A high frequency electronic transducer for multiphase flow measurements

This paper describes an electronic transducer for multiphase flow measurement. Its high sensitivity, good signal to noise ratio and accuracy are achieved through an electrical impedance sensor with a special guard technique. The transducer consists of a wide bandwidth and high slew rate differentiator where the lead inductance and stray capacitance effects are compensated. The sensor edge effect is eliminated by using a guard electrode based on the virtual ground potential of the operational amplifier. A theoretical modeling and a calibration method are also presented. The results obtained seem to confirm the validity of the proposed technique.

An optically coupled power stimulus isolation unit with high voltage and fast rise time output

Recent technological developments have created new devices that could improve and simplify the construction of stimulus isolators. HEXFET transistors can switch large currents and hundreds of volts in nanoseconds. The newer opto-isolators can give a pulse rise time of a few nanoseconds, with output compatible with MOSFET devices, in which delays are reduced to nanoseconds. Integrated DC/DC converters are now available. Using these new resources we developed a new electrical stimulus isolator circuit with selectable constant-current and constant-voltage modes, which are precise and easy to construct. The circuit works like a regulated power supply in both modes with output switched to zero or to free mode through an opto-isolator device. The isolator analyses showed good practical performance. The output to ground resistance was 1011 ohms and capacitance 35 picofarads. The rise time and fall time were identical (5 µs) and constant. The selectable voltage or current output mode made it very convenient to use. The current mode, with higher output resistance values in low current ranges, permits intracellular stimulation even with tip resistances close to 100 megaohms. The high compliance of 200 V guarantees the value of the current stimulus. The very low output resistance in the voltage mode made the device highly suitable for extracellular stimulation with low impedance electrodes. Most importantly, these characteristics were achieved with a circuit that was easy to build and modify and assembled with components available in Brazil.

The influence of high cable penetration in distribution networks on earth fault currents and the operation of relay protection.

Recent Storms in Nordic countries were a reason of long power outages in huge territories. After these disasters distribution networks' operators faced with a problem how to provide adequate quality of supply in such situation. The decision of utilization cable lines rather than overhead lines were made, which brings new features to distribution networks. The main idea of this work is a complex analysis of medium voltage distribution networks with long cable lines. High value of cable’s specific capacitance and length of lines determine such problems as: high values of earth fault currents, excessive amount of reactive power flow from distribution to transmission network, possibility of a high voltage level at the receiving end of cable feeders. However the core tasks was to estimate functional ability of the earth fault protection and the possibility to utilize simplified formulas for operating setting calculations in this network. In order to provide justify solution or evaluation of mentioned above problems corresponding calculations were made and in order to analyze behavior of relay protection principles PSCAD model of the examined network have been created. Evaluation of the voltage rise in the end of a cable line have educed absence of a dangerous increase in a voltage level, while excessive value of reactive power can be a reason of final penalty according to the Finish regulations. It was proved and calculated that for this networks compensation of earth fault currents should be implemented. In PSCAD models of the electrical grid with isolated neutral, central compensation and hybrid compensation were created. For the network with hybrid compensation methodology which allows to select number and rated power of distributed arc suppression coils have been offered. Based on the obtained results from experiments it was determined that in order to guarantee selective and reliable operation of the relay protection should be utilized hybrid compensation with connection of high-ohmic resistor. Directional and admittance based relay protection were tested under these conditions and advantageous of the novel protection were revealed. However, for electrical grids with extensive cabling necessity of a complex approach to the relay protection were explained and illustrated. Thus, in order to organize reliable earth fault protection is recommended to utilize both intermittent and conventional relay protection with operational settings calculated by the use of simplified formulas.

ac conductivity and conduction mechanism of NaNbO3 semiconductor antiferroelectric ceramic: A relaxational approach at high temperature

The electric properties of the sodium niobate perovskite ceramic were investigated by impedance spectroscopy in the frequency range from 5 Hz to 13 MHz and from room temperature up to 1073 K, in a thermal cycle. Both capacitance and conductivity exhibit an anomaly at around 600 K as a function of the temperature and frequency. The electric conductivity as a function of angular frequency sigma(omega) follows the relation sigma(omega)=Aomega(s). The values of the exponent s lie in the range 0.15less than or equal tosless than or equal to0.44. These results were discussed considering the conduction mechanism as being a type of polaron hopping. (C) 2003 American Institute of Physics.

High Curie point CaBi2Nb2O9 thin films: A potential candidate for lead-free thin-film piezoelectrics

CaBi2Nb2O9 (CBNO) thin films deposited on platinum coated silicon substrates by the polymeric precursor method exhibited good structural, dielectric, and piezoelectric characteristics. Capacitance-voltage measurements indicated good ferroelectric polarization switching characteristics. Remanent polarization and drive voltage values were 4.2 mu C/cm(2) and 1.7 V for a maximum applied voltage of 10 V. The film has a piezoelectric coefficient d(33) equal to 60 pm/V, current density of 0.7 mu A/cm(2), and Curie temperature of 940 degrees C. The polar-axis-oriented CBNO is a promising candidate for use in lead-free high Curie point in ferroelectric and piezoelectric devices. (c) 2006 American Institute of Physics.

DESIGN AND FABRICATION OF RESONANT GAS SENSOR FOR HIGH SENSITIVITY IN THE PRESENCE OF AIR DAMPING

Gas sensors have been used widely in different important area including industrial control, environmental monitoring, counter-terrorism and chemical production. Micro-fabrication offers a promising way to achieve sensitive and inexpensive gas sensors. Over the years, various MEMS gas sensors have been investigated and fabricated. One significant type of MEMS gas sensors is based on mass change detection and the integration with specific polymer. This dissertation aims to make contributions to the design and fabrication of MEMS resonant mass sensors with capacitance actuation and sensing that lead to improved sensitivity. To accomplish this goal, the research has several objectives: (1) Define an effective measure for evaluating the sensitivity of resonant mass devices; (2) Model the effects of air damping on microcantilevers and validate models using laser measurement system (3) Develop design guidelines for improving sensitivity in the presence of air damping; (4) Characterize the degree of uncertainty in performance arising from fabrication variation for one or more process sequences, and establish design guidelines for improved robustness. Work has been completed toward these objectives. An evaluation measure has been developed and compared to an RMS based measure. Analytic models of air damping for parallel plate that include holes are compared with a COMSOL model. The models have been used to identify cantilever design parameters that maximize sensitivity. Additional designs have been modeled with COMSOL and the development of an analytical model for Fixed-free cantilever geometries with holes has been developed. Two process flows have been implemented and compared. A number of cantilever designs have been fabricated and the uncertainty in process has been investigated. Variability from processing have been evaluated and characterized.

Transformer modeling ATP : internal faults & high-frequency discretization

Power transformers are key components of the power grid and are also one of the most subjected to a variety of power system transients. The failure of a large transformer can cause severe monetary losses to a utility, thus adequate protection schemes are of great importance to avoid transformer damage and maximize the continuity of service. Computer modeling can be used as an efficient tool to improve the reliability of a transformer protective relay application. Unfortunately, transformer models presently available in commercial software lack completeness in the representation of several aspects such as internal winding faults, which is a common cause of transformer failure. It is also important to adequately represent the transformer at frequencies higher than the power frequency for a more accurate simulation of switching transients since these are a well known cause for the unwanted tripping of protective relays. This work develops new capabilities for the Hybrid Transformer Model (XFMR) implemented in ATPDraw to allow the representation of internal winding faults and slow-front transients up to 10 kHz. The new model can be developed using any of two sources of information: 1) test report data and 2) design data. When only test-report data is available, a higher-order leakage inductance matrix is created from standard measurements. If design information is available, a Finite Element Model is created to calculate the leakage parameters for the higher-order model. An analytical model is also implemented as an alternative to FEM modeling. Measurements on 15-kVA 240?/208Y V and 500-kVA 11430Y/235Y V distribution transformers were performed to validate the model. A transformer model that is valid for simulations for frequencies above the power frequency was developed after continuing the division of windings into multiple sections and including a higher-order capacitance matrix. Frequency-scan laboratory measurements were used to benchmark the simulations. Finally, a stability analysis of the higher-order model was made by analyzing the trapezoidal rule for numerical integration as used in ATP. Numerical damping was also added to suppress oscillations locally when discontinuities occurred in the solution. A maximum error magnitude of 7.84% was encountered in the simulated currents for different turn-to-ground and turn-to-turn faults. The FEM approach provided the most accurate means to determine the leakage parameters for the ATP model. The higher-order model was found to reproduce the short-circuit impedance acceptably up to about 10 kHz and the behavior at the first anti-resonant frequency was better matched with the measurements.

Optimization of the irrigation time and irrigation frequency by using Hydrus-2D and a capacitance FDR sensor

The evolution of water content on a sandy soil during the sprinkler irrigation campaign, in the summer of 2010, of a field of sugar beet crop located at Valladolid (Spain) is assessed by a capacitive FDR (Frequency Domain Reflectometry) EnviroScan. This field is one of the experimental sites of the Spanish research center for the sugar beet development (AIMCRA). The objective of the work focus on monitoring the soil water content evolution of consecutive irrigations during the second two weeks of July (from the 12th to the 28th). These measurements will be used to simulate water movement by means of Hydrus-2D. The water probe logged water content readings (m3/m3) at 10, 20, 40 and 60 cm depth every 30 minutes. The probe was placed between two rows in one of the typical 12 x 15 m sprinkler irrigation framework. Furthermore, a texture analysis at the soil profile was also conducted. The irrigation frequency in this farm was set by the own personal farmer 0 s criteria that aiming to minimizing electricity pumping costs, used to irrigate at night and during the weekend i.e. longer irrigation frequency than expected. However, the high evapotranspiration rates and the weekly sugar beet water consumption—up to 50mm/week—clearly determined the need for lower this frequency. Moreover, farmer used to irrigate for six or five hours whilst results from the EnviroScan probe showed the soil profile reaching saturation point after the first three hours. It must be noted that AIMCRA provides to his members with a SMS service regarding weekly sugar beet water requirement; from the use of different meteorological stations and evapotranspiration pans, farmers have an idea of the weekly irrigation needs. Nevertheless, it is the farmer 0 s decision to decide how to irrigate. Thus, in order to minimize water stress and pumping costs, a suitable irrigation time and irrigation frequency was modeled with Hydrus-2D. Results for the period above mentioned showed values of water content ranging from 35 and 30 (m3/m3) for the first 10 and 20cm profile depth (two hours after irrigation) to the minimum 14 and 13 (m3/m3) ( two hours before irrigation). For the 40 and 60 cm profile depth, water content moves steadily across the dates: The greater the root activity the greater the water content variation. According to the results in the EnviroScan probe and the modeling in Hydrus-2D, shorter frequencies and irrigation times are suggested.

The contribution of sulfate ions and protons to the specific capacitance of microporous carbon monoliths

The monoliths studied in this work show large specific surface areas (up to 1600 m2 g-1), high densities (up to 1.17 g cm-3) and high electrical conductivities (up to 9.5 S cm-1). They are microporous carbons with pore sizes up to 1.3 nm but most of them below 0.75 nm. They also show oxygen functionalities. The electrochemical behavior of the monoliths is studied in three-electrode cells with aqueous H2SO4 solution as electrolyte. This work deals with the contribution of the sulfate ions and protons to the specific capacitance of carbon monoliths having different surface areas and different contents of oxygen groups. Protons contribute with a pseudocapacitance (up to 152 F g-1) in addition to the double layer capacitance. Sulfate ions contribute with a double layer capacitance only. At the double layer, the capacitance of the sulfate ions (up to 291 F g-1) is slightly higher than that of protons (up to 251 F g-1); both capacitances increase as the surface area increases. The preference of protons to be electroadsorbed at the double layer and the broader voltage window of these ions account for their higher contribution (70 %) to the double layer capacitance.

Assembly of a high-dielectric constant thin TiOX layer directly on H-terminated semiconductor diamond

A high-dielectric constant (high-k) TiOx thin layer was fabricated on hydrogen-terminated diamond (H-diamond) surface by low temperature oxidation of a thin titanium layer in ambient air. The metallic titanium layer was deposited by sputter deposition. The dielectric constant of the resultant TiOx was calculated to be around 12. The capacitance density of the metal-oxide-semiconductor (MOS) based on the TiOx/H-diamond was as high as 0.75 µF/cm2 contributed from the high-k value and the very thin thickness of the TiOx layer. The leakage current was lower than 10-13 A at reverse biases and 10-7A at the forward bias of -2 V. The MOS field-effect transistor based on the high-k TiOx/H-diamond was demonstrated. The utilization of the high-k TiOx with a very thin thickness brought forward the features of an ideally low subthreshold swing slope of 65 mV per decade and improved drain current at low gate voltages. The advantages of the utilization high-k dielectric for diamond MOSFETs are anticipated.

DC-link voltage control strategy for reducing capacitance and total harmonic distortion in single-phase grid-connected photovoltaic inverters

High-volume capacitance is required to buffer the power difference between the input and output ports in single-phase grid-connected photovoltaic inverters, which become an obstacle to high system efficiency and long device lifetime. Furthermore, total harmonic distortion becomes serious when the system runs into low power level. In this study, a comprehensive analysis is introduced for two-stage topology with the consideration of active power, DC-link (DCL) voltage, ripple and capacitance. This study proposed a comprehensive DCL voltage control strategy to minimise the DCL capacitance while maintaining a normal system operation. Furthermore, the proposed control strategy is flexible to be integrated with the pulse-skipping control that significantly improves the power quality at light power conditions. Since the proposed control strategy needs to vary DCL voltage, an active protection scheme is also introduced to prevent any voltage violation across the DCL. The proposed control strategy is evaluated by both simulation and experiments, whose results confirm the system effectiveness.

Effects of alternating current voltage amplitude and oxide capacitance on mid-gap interface state defect density extractions in In0.53Ga 0.47As capacitors

This work looks at the effect on mid-gap interface state defect density estimates for In0.53Ga0.47As semiconductor capacitors when different AC voltage amplitudes are selected for a fixed voltage bias step size (100 mV) during room temperature only electrical characterization. Results are presented for Au/Ni/Al2O3/In0.53Ga0.47As/InP metal–oxide–semiconductor capacitors with (1) n-type and p-type semiconductors, (2) different Al2O3 thicknesses, (3) different In0.53Ga0.47As surface passivation concentrations of ammonium sulphide, and (4) different transfer times to the atomic layer deposition chamber after passivation treatment on the semiconductor surface—thereby demonstrating a cross-section of device characteristics. The authors set out to determine the importance of the AC voltage amplitude selection on the interface state defect density extractions and whether this selection has a combined effect with the oxide capacitance. These capacitors are prototypical of the type of gate oxide material stacks that could form equivalent metal–oxide–semiconductor field-effect transistors beyond the 32 nm technology node. The authors do not attempt to achieve the best scaled equivalent oxide thickness in this work, as our focus is on accurately extracting device properties that will allow the investigation and reduction of interface state defect densities at the high-k/III–V semiconductor interface. The operating voltage for future devices will be reduced, potentially leading to an associated reduction in the AC voltage amplitude, which will force a decrease in the signal-to-noise ratio of electrical responses and could therefore result in less accurate impedance measurements. A concern thus arises regarding the accuracy of the electrical property extractions using such impedance measurements for future devices, particularly in relation to the mid-gap interface state defect density estimated from the conductance method and from the combined high–low frequency capacitance–voltage method. The authors apply a fixed voltage step of 100 mV for all voltage sweep measurements at each AC frequency. Each of these measurements is repeated 15 times for the equidistant AC voltage amplitudes between 10 mV and 150 mV. This provides the desired AC voltage amplitude to step size ratios from 1:10 to 3:2. Our results indicate that, although the selection of the oxide capacitance is important both to the success and accuracy of the extraction method, the mid-gap interface state defect density extractions are not overly sensitive to the AC voltage amplitude employed regardless of what oxide capacitance is used in the extractions, particularly in the range from 50% below the voltage sweep step size to 50% above it. Therefore, the use of larger AC voltage amplitudes in this range to achieve a better signal-to-noise ratio during impedance measurements for future low operating voltage devices will not distort the extracted interface state defect density.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.