921 resultados para HIGH-GAIN


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A simple design for a low-profile high-gain planar antenna has been presented in the letter. The antenna has the realized gain between 9 and 11 dBi and the return loss better than 10 dB over the 5.6-6.3-GHz frequency band, i.e. 11% bandwidth. A numerical study highlighting effects of key geometrical parameters on the gain and return loss of the antenna has been performed. It has been shown as well that the presented antenna occupies area 20% smaller than a conventional microstrip patch antenna array with a similar gain.

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Evidence of high gain pumped by recombination has been observed in the 5g-4f transition at 11.1 nn in sodiumlike copper ions with use of a 20-J 2-ps Nd:glass laser system. The time- and space-integrated gain coefficient was 8.8 +/- 1.4 cm(-1), indicating a single-transit amplification of similar to 60 times. This experiment has shown that 2 ps is the optimum pulse duration to drive the sodiumlike copper recombination x-ray lasing at 11.1 nm. (C) 1996 Optical Society of America

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Recombining plasmas produced by picosecond laser pulses are characterized by measuring ratio of intensities of resonance lines of H- and He-like ions in the plasmas. It is found that the rapidly recombining plasmas produced by picosecond laser pulses are suitable for high-gain operation.

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This article proposes a frequency agile antenna whose operating frequency band can be switched. The design is based on a Vivaldi antenna. High-performance radio-frequency microelectromechanical system (RF-MEMS) switches are used to realize the 2.7 GHz and 3.9 GHz band switching. The low band starts from 2.33 GHz and works until 3.02 GHz and the high band ranges from 3.29 GHz up to 4.58 GHz. The average gains of the antenna at the low and high bands are 10.9 and 12.5 dBi, respectively. This high-gain frequency reconfigurable antenna could replace several narrowband antennas for reducing costs and space to support multiple communication systems, while maintaining good performance.

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Technology scaling has enabled drastic growth in the computational and storage capacity of integrated circuits (ICs). This constant growth drives an increasing demand for high-bandwidth communication between and within ICs. In this dissertation we focus on low-power solutions that address this demand. We divide communication links into three subcategories depending on the communication distance. Each category has a different set of challenges and requirements and is affected by CMOS technology scaling in a different manner. We start with short-range chip-to-chip links for board-level communication. Next we will discuss board-to-board links, which demand a longer communication range. Finally on-chip links with communication ranges of a few millimeters are discussed.

Electrical signaling is a natural choice for chip-to-chip communication due to efficient integration and low cost. IO data rates have increased to the point where electrical signaling is now limited by the channel bandwidth. In order to achieve multi-Gb/s data rates, complex designs that equalize the channel are necessary. In addition, a high level of parallelism is central to sustaining bandwidth growth. Decision feedback equalization (DFE) is one of the most commonly employed techniques to overcome the limited bandwidth problem of the electrical channels. A linear and low-power summer is the central block of a DFE. Conventional approaches employ current-mode techniques to implement the summer, which require high power consumption. In order to achieve low-power operation we propose performing the summation in the charge domain. This approach enables a low-power and compact realization of the DFE as well as crosstalk cancellation. A prototype receiver was fabricated in 45nm SOI CMOS to validate the functionality of the proposed technique and was tested over channels with different levels of loss and coupling. Measurement results show that the receiver can equalize channels with maximum 21dB loss while consuming about 7.5mW from a 1.2V supply. We also introduce a compact, low-power transmitter employing passive equalization. The efficacy of the proposed technique is demonstrated through implementation of a prototype in 65nm CMOS. The design achieves up to 20Gb/s data rate while consuming less than 10mW.

An alternative to electrical signaling is to employ optical signaling for chip-to-chip interconnections, which offers low channel loss and cross-talk while providing high communication bandwidth. In this work we demonstrate the possibility of building compact and low-power optical receivers. A novel RC front-end is proposed that combines dynamic offset modulation and double-sampling techniques to eliminate the need for a short time constant at the input of the receiver. Unlike conventional designs, this receiver does not require a high-gain stage that runs at the data rate, making it suitable for low-power implementations. In addition, it allows time-division multiplexing to support very high data rates. A prototype was implemented in 65nm CMOS and achieved up to 24Gb/s with less than 0.4pJ/b power efficiency per channel. As the proposed design mainly employs digital blocks, it benefits greatly from technology scaling in terms of power and area saving.

As the technology scales, the number of transistors on the chip grows. This necessitates a corresponding increase in the bandwidth of the on-chip wires. In this dissertation, we take a close look at wire scaling and investigate its effect on wire performance metrics. We explore a novel on-chip communication link based on a double-sampling architecture and dynamic offset modulation technique that enables low power consumption and high data rates while achieving high bandwidth density in 28nm CMOS technology. The functionality of the link is demonstrated using different length minimum-pitch on-chip wires. Measurement results show that the link achieves up to 20Gb/s of data rate (12.5Gb/s/$\mu$m) with better than 136fJ/b of power efficiency.

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Planar punch through heterojunction phototransistors with a novel emitter control electrode and ion- implanted isolation (CE-PTHPT) are investigated. The phototransistors have a working voltage of 3-10V and high sensitivity at low input power. The base of the transistor is completely depleted under operating condition. Base current is zero. The CE-PTHPT has an increased speed and a decreased noise. The novel CE-PTHPT has been fabricated in this paper. The optical gain of GaAlAs/GaAs CE-PTHPT for the incident light power 1.3 and 43nw with the wavelength of 0.8 mu m reached 1260 and 8108. The input noise current calculated is 5.46 x 10(-16) A/H-z(1/2). For polysilicon emitter CE-PTHPT, the optical gain is 3083 at the input power of 0.174 mu w. The optical gain of InGaAs/InP CE-PTHPT reaches 350 for an incident power of 0.3 mu w at the wavelength of 1.55 mu m. The CE-PTHPT detectors is promising as photo detectors for optical fiber communication system.

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In order to realize the common-emitter characteristics of the tris(8-hydroxyquinoline) aluminium (Alq(3))-based organic transistors, we used Au/Al double metal layer as the base, thus the vertical metal-base transistors with structure of Al/n-Si/Au/Al/Alq(3)/LiF/Al were constructed. It was found that the contact properties between the base and the organic semiconductors play an important role in the device performance. The utilization of Au/Al double layer metal base allows the devices to operate at high gain in the common-emitter and common-base mode at low operational voltage.

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We demonstrate the suitability of N,N'-diphenyl-N,N'-bis(1-naphthylphenyl)-1,1'-biphenyl-4,4'-diamine (NPB), an organic semiconductor widely used in organic light-emitting diodes (OLEDs), for high-gain, low operational voltage nanostructured vertical-architecture transistors, which operate as permeable-base transistors. By introducing vanadium oxide (V2O5) between the injecting metal and NPB layer at the transistor emitter, we reduced the emitter operational voltage.