ASIC microcontroller design of a radiation monitoring system using VHDL modeling and FPGA implementation

Three new technologies have been brought together to develop a miniaturized radiation monitoring system. The research involved (1) Investigation a new HgI$\sb2$ detector. (2) VHDL modeling. (3) FPGA implementation. (4) In-circuit Verification. The packages used included an EG&G's crystal(HgI$\sb2$) manufactured at zero gravity, the Viewlogic's VHDL and Synthesis, Xilinx's technology library, its FPGA implementation tool, and a high density device (XC4003A). The results show: (1) Reduced cycle-time between Design and Hardware implementation; (2) Unlimited Re-design and implementation using the static RAM technology; (3) Customer based design, verification, and system construction; (4) Well suited for intelligent systems. These advantages excelled conventional chip design technologies and methods in easiness, short cycle time, and price in medium sized VLSI applications. It is also expected that the density of these devices will improve radically in the near future. ^

The Spartan-3E Tutorial 1 : Introduction to FPGA Programming, Version 1.0

This tutorial is designed to help new users become familiar with using the Spartan-3E board. The tutorial steps through the following: writing a small program in VHDL which carries out simple combinational logic; connecting the program inputs and outputs to the switches, buttons and LEDs on the Spartan-3E board; and downloading the program to the Spartan-3E board using the Project Navigator software.

The Spartan-3E Tutorial 1 : Introduction to FPGA Programming, Version 2.0

This tutorial is designed to help new users become familiar with using the Spartan-3E board. The tutorial steps through: writing a small program in VHDL which carries out simple combinational logic; connecting the program inputs and outputs to the switches, buttons and LEDs on the Spartan-3E board; downloading the program to the Spartan-3E board using version 14.7 of the Xilinx ISE; and simulating the program using the iSim Simulator.

Generación automática de VHDL mediante Simulink HDL coder y aplicación al procesado de señales

Gordon E. Moore, co-fundador de Intel, predijo en una publicación del año 1965 que aproximadamente cada dos años se duplicaría el número de transistores presentes en un circuito integrado, debido a las cada vez mejores tecnologías presentes en el proceso de elaboración. A esta ley se la conoce como Ley de Moore y su cumplimiento se ha podido constatar hasta hoy en día. Gracias a ello, con el paso del tiempo cada vez se presentan en el mercado circuitos integrados más potentes, con mayores prestaciones para realizar tareas cada vez más complejas. Un tipo de circuitos integrados que han podido evolucionar de forma importante por dicho motivo, son los dispositivos de lógica programable, circuitos integrados que permiten implementar sobre ellos las funciones lógicas que desee implementar el usuario. Hasta hace no muchos años, dichos dispositivos eran capaces de implementar circuitos compuestos por unas pocas funciones lógicas, pero gracias al proceso de miniaturización predicho por la Ley de Moore, hoy en día son capaces de implementar circuitos tan complejos como puede ser un microprocesador; dichos dispositivos reciben el nombre de FPGA, siglas de Field Programmable Gate Array. Debido a la mayor capacidad y por lo tanto a diseños más complejos implementados sobre las FPGA, en los últimos años han aparecido herramientas cuyo objetivo es hacer más fácil el proceso de ingeniería dentro de un desarrollo en este tipo de dispositivos, como es la herramienta HDL Coder de la compañía MathWorks, creadores también Matlab y Simulink, unas potentes herramientas usadas ampliamente en diferentes ramas de la ingeniería. El presente proyecto tiene como objetivo evaluar el uso de dicha herramienta para el procesado digital de señales, usando para ello una FPGA Cyclone II de la casa Altera. Para ello, se empezará analizando la herramienta escogida comparándola con herramientas de la misma índole, para a continuación seleccionar una aplicación de procesado digital de señal a implementar. Tras diseñar e implementar la aplicación escogida, se deberá simular en PC para finalmente integrarla en la placa de evaluación seleccionada y comprobar su correcto funcionamiento. Tras analizar los resultados de la aplicación de implementada, concretamente un analizador de la frecuencia fundamental de una señal de audio, se ha comprobado que la herramienta HDL Coder, es adecuada para este tipo de desarrollos, facilitando enormemente los procesos tanto de implementación como de validación gracias al mayor nivel de abstracción que aporta.

用VHDL实现的23位快速浮点数加减法器

With the development of LSI, FPGA/CPLD has been used more and more in the fields of digital signal processing and au-tocontrol and so on. And with the development of the techniques of digital processing, for fitting the system’s function, it should be a higher requirement to speed and used-resource to compute the floating point numbers. The author introduces a high speed adder-subtracter of the 23 bit’s floating point numbers, which is carried out with the parallel arithmetic and the computational speed cou...中文文摘：随着大规模集成电路的不断发展,FPGA/CPLD在数字信号处理、自动控制等方面得到了越来越多的应用。并且伴随着数字化处理技术的不断发展,为满足系统功能的要求,对浮点数运算的速度以及相应占用的资源也就提出了更高的要求。笔者即介绍了以VHDL语言为基础,采用并行算法且计算速度达到33MHz的,对23位标准浮点数实现的高速浮点加减法运算器,并以Cyclone II芯片EP2C20F484为硬件环境,最终进行时序模拟仿真,从而验证该浮点加减法器的正确性和快速特性。

一种FPGA的嵌入式可重构机器人控制系统

提出一种基于FPGA的可重构嵌入式微处理器控制系统.在FPGA中嵌入两个NiosⅡ软核,用VHDL语言编写用户自定义组件.在一个由NiosⅡ软核组成的处理器上实现PWM信号生成、编码器信号处理以及多电机同步伺服运算等,在另一个处理器实现机器人任务管理.该控制系统针对微小型爬壁机器人的控制系统设计,不仅具有良好的实时多任务处理能力,而且具有可重构的特点,因而可应用于一类微小型机器人控制系统以提高其设计的灵活性.

Efficient FPGA Hardware Development: A Multi-Language Approach

This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high-level hardware design and efficient hardware implementation. The central idea of this framework is the integration of different hardware languages in a way that harnesses the best features of each language. This is illustrated in this paper by the integration of two hardware languages in the form of HIDE: a structured hardware language which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog, and Handel-C: an ANSI C-like hardware language which allows software and hardware engineers alike to target FPGAs from high-level algorithmic descriptions. On the one hand, HIDE has proven to be very successful in the description and generation of highly optimised parameterisable FPGA circuits from geometric descriptions. On the other hand, Handel-C has also proven to be very successful in the rapid design and prototyping of FPGA circuits from algorithmic application descriptions. The proposed integrated framework hence harnesses HIDE for the generation of highly optimised circuits for regular parts of algorithms, while Handel-C is used as a top-level design language from which HIDE functionality is dynamically invoked. The overall message of this paper posits that there need not be an exclusive choice between different hardware design flows. Rather, an integrated framework where different design flows can seamlessly interoperate should be adopted. Although the idea might seem simple prima facie, it could have serious implications on the design of future generations of hardware languages.

Design of a Multiband Full-Rate Ultra-Wideband Receiver in FPGA

MultiBand OFDM (MB-OFDM) UWB [1] is a short-range promising wireless technology for high data rate communications up to 480 Mbps. In this paper, we have designed and implemented in an Virtex-6 FPGA an MB-OFDM UWB receiver for the highest data rate of 480 Mbps. To test the system, we have also implemented an MB-OFDM transmitter and an AWGN generator in VHDL and determined the bit error rates at the receiver running in an FPGA.

Design et implémentation sur FPGA d'un algorithme DES

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal

Sincronização de múltiplas câmaras e controlo de iluminação sobre uma plataforma FPGA

O objetivo deste projeto foi o de realizar a sincronização de pelo menos quatro câmaras individuais, ajustando dinamicamente o frame rate de operação de cada câmara, tendo por base a família de sensores de imagem CMOS NanEye da empresa Awaiba, numa plataforma FPGA com interface USB3. Durante o projeto analisou-se, com a assistência de um supervisor da Awaiba, o sistema core de captura de imagem existente, baseado em VHDL. Foi estudado e compreendido o princípio do ajuste dinâmico do frame rate das câmaras. Tendo sido então desenvolvido o módulo de controlo da câmara, em VHDL, e um algoritmo de ajuste dinâmico do frame rate, sendo este implementado junto com a plataforma de processamento e interface da FPGA. Foi criado um módulo para efetuar a monitorização da frequência de operação de cada câmara, medindo o período de cada linha numa frame, tendo por base um sinal de relógio de valor conhecido. A frequência é ajustada variando o nível de tensão aplicado ao sensor com base no erro entre o período da linha medido e o período pretendido. Para garantir o funcionamento conjunto de múltiplas câmaras em modo síncrono foi implementada uma interface Master-Slave entre estas. Paralelamente ao módulo anteriormente descrito, implementou-se um sistema de controlo automático de iluminação com base na análise de regiões de interesse em cada frame captada por uma câmara NanEye. A intensidade de corrente aplicada às fontes de iluminação acopladas à câmara é controlada dinamicamente com base no nível de saturação dos pixéis analisados em cada frame. Foram desenvolvidas e implementadas variantes do algoritmo de controlo e o seu desempenho foi avaliado em laboratório. Os resultados obtidos na prática evidenciam que a solução implementada cumpre os requisitos de controlo e ajuste da frequência de operação de múltiplas câmaras. Mostrou ser um método de controlo capaz de manter um erro de sincronização médio de 3,77 μs mesmo na presença de variações de temperatura de aproximadamente 50 °C. Foi também demonstrado que o sistema de controlo de iluminação é capaz de proporcionar uma experiência de visualização adequada, alcançando erros menores que 3% e uma velocidade de ajuste máxima inferior a 1 s.

A 2kW interleaved ZCS-FM boost rectifier digitally controlled by FPGA device

This paper presents a 2kW single-phase high power factor boost rectifier with four cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by Field Programmable Gate Array (FPGA). The soft-switching technique Is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-voltage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related 'to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the Interleaving technique, the rectifer's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) In the input current, in compliance with the TEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for four interleaved cells, and a closed-loop to provide the output voltage regulation, like as a pre-regulator rectifier. Experimental results are presented for a 2kW implemented prototype with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.

A VHDL-based protocol controller for NCAP processors

This work presents the development of an IEEE 1451.2 protocol controller based on a low-cost FPGA that is directly connected to the parallel port of a conventional personal computer. In this manner it is possible to implement a Network Capable Application Processor (NCAP) based on a personal computer, without parallel port modifications. This approach allows supporting the ten signal lines of the 10-wire IEEE 1451.2 Transducer Independent Interface (TII), that connects the network processor to the Smart Transducer Interface Module (STIM) also defined in the IEEE 1451.2 standard. The protocol controller is connected to the STIM through the TII's physical interface, enabling the portability of the application at the transducer and network processor level. The protocol controller architecture was fully developed in VHDL language and we have projected a special prototype configured in a general-purpose programmable logic device. We have implemented two versions of the protocol controller, which is based on IEEE 1451 standard, and we have obtained results using simulation and experimental tests. (c) 2008 Elsevier B.V. All rights reserved.

A multi-cell variable frequency interleaved ZCS boost rectifier digitally controlled by FPGA

This paper presents a multi-cell single-phase high power factor boost rectifier in interleave connection, operating in critical conduction mode, employing a soft-switching technique, and controlled by Field Programmable Gate Array (FPGA). The soft-switching technique is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-vohage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the interleaving technique, the rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the IEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for all interleaved cells, and a closed-loop to provide the output voltage regulation, like as a preregulator rectifier. Experimental results are presented for a implemented prototype with two and with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.

A phase-shifting control for variable frequency multi-cells interleaved boost pre-regulator based on FPGA device

In this paper were investigated phase-shift control strategies applied to a four cells interleaved high input-power-factor pre-regulator boost rectifier, operating in critical conduction mode, using a non-dissipative commutation cells and frequency modulation. The digital control has been developed using a hardware description language (VHDL) and implemented using the XC2S200E-SpartanII-E/Xilinx FPGA, performing a true critical conduction operation mode for a generic number of interleaved cells. Experimental results are presented, in order to verify the feasibility and performance of the proposed digital control, through the use of a Xilinx FPGA device.

An AC voltage regulator with high-power-factor, and control using a FPGA device

This paper presents the analysis, design, simulation, and experimental results for a high frequency high Power-Factor (PF) AC (Alternate Current) voltage regulator, using a Sepic converter as power stage. The control technique employed to impose a sinusoidal input current waveform, with low Total Harmonic Distortion (THD), is the sinusoidal variable hysteresis control. The control technique was implemented in a FPGA (Field Programmable Gate Array) device, using a Hardware Description Language (VHDL). Through the use of the proposed control technique, the AC voltage regulator performs active power-factor correction, and low THD in the input current, for linear and non-linear loads, satisfying the requirements of the EEC61000-3-2 standards. Experimental results from an example prototype, designed for 300W of nominal output power, 50kHz (switching frequency), and 127Vrms of nominal input and output voltages, are presented in order to validate the proposed AC regulator. © 2005 IEEE.