Multiple synchronous states in static delay-free mutually connected PLL networks

In many engineering applications, the time coordination of geographically separated events is of fundamental importance, as in digital telecommunications and integrated digital circuits. Mutually connected (MC) networks are very good candidates for some new types of application, such as wireless sensor networks. This paper presents a study on the behavior of MC networks of digital phase-locked loops (DPLLs). Analytical results are derived showing that, even for static networks without delays, different synchronous states may exist for the network. An upper bound for the number of such states is also presented. Numerical simulations are used to show the following results: (i) the synchronization precision in MC DPLLs networks; (ii) the existence of synchronous states for the network does not guarantee its achievement and (iii) different synchronous states may be achieved for different initial conditions. These results are important in the neural computation context. as in this case, each synchronous state may be associated to a different analog memory information. (C) 2010 Elsevier B.V. All rights reserved.

WCET analysis considering contention on memory bus in COTS-based multicores

The usage of COTS-based multicores is becoming widespread in the field of embedded systems. Providing realtime guarantees at design-time is a pre-requisite to deploy real-time systems on these multicores. This necessitates the consideration of the impact of the contention due to shared low-level hardware resources on the Worst-Case Execution Time (WCET) of the tasks. As a step towards this aim, this paper first identifies the different factors that make the WCET analysis a challenging problem in a typical COTS-based multicore system. Then, we propose and prove, a mathematically correct method to determine tight upper bounds on the WCET of the tasks, when they are co-scheduled on different cores.

CPMD-mindful task assignment for NPS-F

The multiprocessor scheduling scheme NPS-F for sporadic tasks has a high utilisation bound and an overall number of preemptions bounded at design time. NPS-F binpacks tasks offline to as many servers as needed. At runtime, the scheduler ensures that each server is mapped to at most one of the m processors, at any instant. When scheduled, servers use EDF to select which of their tasks to run. Yet, unlike the overall number of preemptions, the migrations per se are not tightly bounded. Moreover, we cannot know a priori which task a server will be currently executing at the instant when it migrates. This uncertainty complicates the estimation of cache-related preemption and migration costs (CPMD), potentially resulting in their overestimation. Therefore, to simplify the CPMD estimation, we propose an amended bin-packing scheme for NPS-F allowing us (i) to identify at design time, which task migrates at which instant and (ii) bound a priori the number of migrating tasks, while preserving the utilisation bound of NPS-F.

NoC contention analysis using a branch-and-prune algorithm

“Many-core” systems based on a Network-on-Chip (NoC) architecture offer various opportunities in terms of performance and computing capabilities, but at the same time they pose many challenges for the deployment of real-time systems, which must fulfill specific timing requirements at runtime. It is therefore essential to identify, at design time, the parameters that have an impact on the execution time of the tasks deployed on these systems and the upper bounds on the other key parameters. The focus of this work is to determine an upper bound on the traversal time of a packet when it is transmitted over the NoC infrastructure. Towards this aim, we first identify and explore some limitations in the existing recursive-calculus-based approaches to compute the Worst-Case Traversal Time (WCTT) of a packet. Then, we extend the existing model by integrating the characteristics of the tasks that generate the packets. For this extended model, we propose an algorithm called “Branch and Prune” (BP). Our proposed method provides tighter and safe estimates than the existing recursive-calculus-based approaches. Finally, we introduce a more general approach, namely “Branch, Prune and Collapse” (BPC) which offers a configurable parameter that provides a flexible trade-off between the computational complexity and the tightness of the computed estimate. The recursive-calculus methods and BP present two special cases of BPC when a trade-off parameter is 1 or ∞, respectively. Through simulations, we analyze this trade-off, reason about the implications of certain choices, and also provide some case studies to observe the impact of task parameters on the WCTT estimates.

Influência do tipo de adesivo em juntas híbridas soldadas-adesivas

A necessidade de utilizar métodos de ligação entre componentes de forma mais rápida, eficaz e com melhores resultados, tem causado a crescente utilização das juntas adesivas, em detrimento dos métodos tradicionais de ligação tais como a soldadura, brasagem, ligações aparafusadas e rebitadas. A utilização das juntas adesivas tem vindo a aumentar em diversas aplicações industriais por estas apresentarem vantagens das quais se destacam a redução de peso, redução de concentrações de tensões e facilidade de fabrico. No entanto, também apresentam desvantagens, como a necessidade de preparação das juntas e o descentramento da carga aplicada que provoca efeitos de flexão, os quais dão origem a tensões normais na direcção da espessura do adesivo (tensões de arrancamento), afectando assim a resistência da junta. A combinação da ligação adesiva com a soldadura por pontos permite algumas vantagens em comparação com as juntas adesivas tradicionais como a maior resistência, aumento da rigidez, melhor resistência ao corte e arrancamento e também à fadiga. Neste trabalho é apresentado um estudo experimental e numérico de juntas de sobreposição simples adesivas e híbridas (adesivas-soldadas). Os adesivos utilizados são o Araldite AV138®, apresentado como sendo frágil, e os adesivos Araldite 2015® e Sikaforce® 7752, intitulados como adesivos dúcteis. Foram considerados substratos de aço (C45E) em juntas com diferentes comprimentos de sobreposição ( ), que foram sujeitas a esforços de tracção. Foi realizada uma análise dos valores experimentais e efectuada uma comparação destes valores com os resultados obtidos por Elementos Finitos (EF) no software ABAQUS®, que incluiu uma análise de tensões na camada de adesivo e previsão do comportamento das juntas por Modelos de Dano Coesivo (MDC). A análise por MDC permitiu obter os modos de rotura, as curvas força-deslocamento e a resistência das juntas com bastante precisão, com excepção das juntas coladas com o adesivo Sikaforce® 7752. Estes resultados permitiram validar a técnica de modelação proposta para as juntas coladas e híbridas, o que representa uma base para posterior aplicação desta técnica em projecto, com as vantagens decorrentes da redução do tempo de projecto e maior facilidade de optimização.

Scalable and Efficient Configuration of TimeDivision Multiplexed Resources

Consumer-electronics systems are becoming increasingly complex as the number of integrated applications is growing. Some of these applications have real-time requirements, while other non-real-time applications only require good average performance. For cost-efficient design, contemporary platforms feature an increasing number of cores that share resources, such as memories and interconnects. However, resource sharing causes contention that must be resolved by a resource arbiter, such as Time-Division Multiplexing. A key challenge is to configure this arbiter to satisfy the bandwidth and latency requirements of the real-time applications, while maximizing the slack capacity to improve performance of their non-real-time counterparts. As this configuration problem is NP-hard, a sophisticated automated configuration method is required to avoid negatively impacting design time. The main contributions of this article are: 1) An optimal approach that takes an existing integer linear programming (ILP) model addressing the problem and wraps it in a branch-and-price framework to improve scalability. 2) A faster heuristic algorithm that typically provides near-optimal solutions. 3) An experimental evaluation that quantitatively compares the branch-and-price approach to the previously formulated ILP model and the proposed heuristic. 4) A case study of an HD video and graphics processing system that demonstrates the practical applicability of the approach.

Passive Fault-Tolerance Management in Component-based Embedded Systems

It is imperative to accept that failures can and will occur, even in meticulously designed distributed systems, and design proper measures to counter those failures. Passive replication minimises resource consumption by only activating redundant replicas in case of failures, as typically providing and applying state updates is less resource demanding than requesting execution. However, most existing solutions for passive fault tolerance are usually designed and configured at design time, explicitly and statically identifying the most critical components and their number of replicas, lacking the needed flexibility to handle the runtime dynamics of distributed component-based embedded systems. This paper proposes a cost-effective adaptive fault tolerance solution with a significant lower overhead compared to a strict active redundancy-based approach, achieving a high error coverage with the minimum amount of redundancy. The activation of passive replicas is coordinated through a feedback-based coordination model that reduces the complexity of the needed interactions among components until a new collective global service solution is determined, improving the overall maintainability and robustness of the system.

Estudo e otimização de juntas do tipo Tpeel soldadas, adesivas e híbridas

A necessidade de utilizar métodos de ligação que melhor satisfaçam as necessidades de projeto tem causado a crescente utilização das juntas adesivas, em detrimento dos métodos tradicionais tais como a soldadura, ligações aparafusadas e rebitadas. A sua utilização em diversas aplicações industriais justifica-se pela redução de peso, redução de concentrações de tensões, isolamento acústico e melhor resistência à corrosão. Contudo, também apresentam desvantagens, como a necessidade de preparação das juntas, a fraca resistência a esforços de arrancamento e a complexidade da previsão da sua resistência. As juntas híbridas são obtidas por combinação de uma técnica tradicional com uma ligação adesiva. As juntas híbridas adesivas-soldadas obtêm-se através da combinação da ligação adesiva com a ligação soldada, sendo a soldadura de resistência por pontos a técnica de soldadura mais usada no fabrico deste tipo de juntas. A sinergia entre ligação adesiva e soldadura por pontos oferece vantagens competitivas em relação às ligações adesivas, tais como superior resistência e rigidez, e maior resistência ao arrancamento e à fadiga. No presente trabalho é apresentado um estudo experimental e numérico de juntas T-peel soldadas, adesivas e híbridas (adesivas-soldadas) solicitadas ao arrancamento. Considerouse o adesivo frágil Araldite® AV138 e os adesivos dúcteis Araldite® 2015 e Sikaforce® 7752 e aderentes de aço (C45E). Foi realizada uma análise dos valores experimentais e efetuada uma comparação destes valores com os resultados obtidos pelo Método de Elementos Finitos (MEF) no software ABAQUS®, que incluiu uma análise de tensões na camada de adesivo e previsão do comportamento das juntas por MDC. Observou-se que, dos três adesivos em estudo, o adesivo Sikaforce® 7752 é o que apresenta o melhor desempenho na ligação de juntas T-peel. A boa concordância entre os resultados experimentais e numéricos permitiu validar a utilização de MDC para previsão da resistência de juntas T-peel adesivas e híbridas. Assim, o presente trabalho representa uma base para posterior aplicação no projeto deste tipo de ligação, com as vantagens decorrentes na redução do tempo de projeto e maior facilidade de otimização.

Interoperability on low power devices

Dissertação para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores

Quality of process modeling using BPMN: a model-driven approach

Dissertação para obtenção do Grau de Doutor em Engenharia Informática

Scheduling in virtual infrastructure

For the execution of the scientific applications, different methods have been proposed to dynamically provide execution environments for such applications that hide the complexity of underlying distributed and heterogeneous infrastructures. Recently virtualization has emerged as a promising technology to provide such environments. Virtualization is a technology that abstracts away the details of physical hardware and provides virtualized resources for high-level scientific applications. Virtualization offers a cost-effective and flexible way to use and manage computing resources. Such an abstraction is appealing in Grid computing and Cloud computing for better matching jobs (applications) to computational resources. This work applies the virtualization concept to the Condor dynamic resource management system by using Condor Virtual Universe to harvest the existing virtual computing resources to their maximum utility. It allows existing computing resources to be dynamically provisioned at run-time by users based on application requirements instead of statically at design-time thereby lay the basis for efficient use of the available resources, thus providing way for the efficient use of the available resources.

Redefinición del interfaz del Centro de Tráfico Centralizado (CTC) de una explotación ferroviaria

En aquest projecte, es mira de reflectir la necessitat d'utilitzar l'enginyeria i la facilitat d'ús per millorar els sistemes de control en temps real que es fan servir avui dia per a controlar processos crítics.

Three-dimensional computed cementless custom femoral stems in young patients: midterm followup.

We prospectively evaluated the results of our custom cementless femoral stems to ascertain whether this technology produced reasonable clinical function, complication rates, and loosening rates at midterm. Fifty-seven consecutive patients had surgery in 62 hips for primary osteoarthritis at a mean age of 57 years using a three-dimensional computed custom cementless stem. Patients were reviewed at a mean followup of 94.9 months. At review, the mean Harris hip score was 98.8 points (range, 84-100) compared with 61.1 (range, 28-78) points preoperatively. No patient complained of thigh pain. No migration or subsidence was observed. All stems were considered stable according to the radiographic criteria defined by Engh et al. There were no dislocations, no infections, and no reoperations. Our results are comparable with published results from clinical and radiologic points of view. Two problems remain unsolved: the price of a custom stem is twice as expensive as a standard stem; and we need longer term results before definitely recommending this technology as a reasonable alternative to current arthroplasties in younger patients. The data support the continued exploration of this technology with controlled clinical followup. LEVEL OF EVIDENCE: Therapeutic study, Level II-1 (prospective cohort study). See the Guidelines to Authors for a complete description of levels of evidence.

Tuotealustapohjaisen suunnittelun vaikutukset risteilijän suunnitteluaikatauluihin

Tuotealustapohjaisella suunnittelulla pyritään hyödyntämään jo kertaalleen hyväksi todettuja kokonaisuuksia ja moduuleja, joiden avulla voidaan nopeasti suunnitella uusia tuotteita. Tarkoituksena on suunnitella asiakkaan näkökulmasta monia erilaisia tuotteita jopa sarjatuotannon kustannustehokkuudella. Tutkimuksessa esitetään risteilijän tuotealustapohjainen suunnitteluprosessi. Lisäksi työn tavoitteena on tutkia uuden suunnitteluprosessin vaikutukset risteilijän suunnitteluaikatauluihin. Tutkimuksessa haastateltiin Turun telakan suunnitteluosaston ja kehitysosaston johtajia. Haastatteluilla selvitettiin nykyisen suunnitteluprosessin haasteita, joiden nähtiin erityisesti viivästyttävät suunnitteluaikatauluja. Keskeisiä haasteita ovat suunnitteluresurssien ylikuormitus ja suunnittelulaadun huonontuminen. Lisäksi kartoitettiin tavoitteet risteilijän tuotealustaratkaisulle ja suunnitteluaikataululle. Haastattelukierroksen pohjalta ja teoriaa soveltaen analysoitiin risteilijän modulaariseen tuotealustaan perustuva suunnitteluprosessi. Tätä suunnitteluprosessia tutkittiin edelleen case-tutkimuksessa jääasemien osalta, jossa haastateltiin kyseisten alueiden suunnittelijoita. Lisäksi case-tutkimuksessa verrattiin jääaseman ja baaripentterin perussuunnittelun vaiheita toisiinsa. Näistä saatuja tutkimustuloksia verrattiin hyttialueen vakioidun perussuunnitteluohjeen vaikutuksiin suunnitteluprosessissa. Onnistunut tuotealustapohjainen suunnittelu vaatii sitoutumista jokaisella organisaation tasolla, jotta tuotealustassa olevien vakioituja moduuleja myös käytettäisiin. Modulaarisesta toiminnasta siirtyminen tuotealustapohjaiseen suunnitteluun vaatii vakioituja moduuleja ja vakioituja rajapintoja risteilijässä. Case-tutkimuksessa ja johtopäätöksissä on todettu uuden suunnitteluprosessin lyhentävän ja tuovan kustannussäästöjä tuotteen valmistusprosessissa.

Thermal-Aware Networked Many-Core Systems

Advancements in IC processing technology has led to the innovation and growth happening in the consumer electronics sector and the evolution of the IT infrastructure supporting this exponential growth. One of the most difficult obstacles to this growth is the removal of large amount of heatgenerated by the processing and communicating nodes on the system. The scaling down of technology and the increase in power density is posing a direct and consequential effect on the rise in temperature. This has resulted in the increase in cooling budgets, and affects both the life-time reliability and performance of the system. Hence, reducing on-chip temperatures has become a major design concern for modern microprocessors. This dissertation addresses the thermal challenges at different levels for both 2D planer and 3D stacked systems. It proposes a self-timed thermal monitoring strategy based on the liberal use of on-chip thermal sensors. This makes use of noise variation tolerant and leakage current based thermal sensing for monitoring purposes. In order to study thermal management issues from early design stages, accurate thermal modeling and analysis at design time is essential. In this regard, spatial temperature profile of the global Cu nanowire for on-chip interconnects has been analyzed. It presents a 3D thermal model of a multicore system in order to investigate the effects of hotspots and the placement of silicon die layers, on the thermal performance of a modern ip-chip package. For a 3D stacked system, the primary design goal is to maximise the performance within the given power and thermal envelopes. Hence, a thermally efficient routing strategy for 3D NoC-Bus hybrid architectures has been proposed to mitigate on-chip temperatures by herding most of the switching activity to the die which is closer to heat sink. Finally, an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems has been presented. Various thermal models have been developed and thermal control metrics have been extracted. An efficient thermal-aware application mapping algorithm for a 2D NoC has been presented. It has been shown that the proposed mapping algorithm reduces the effective area reeling under high temperatures when compared to the state of the art.