The coder : a program module for code generation in high-level language compilers /

Originally presented as the author's thesis (M.S.), University of Illinois at Urbana-Champaign.

Supporting the Model-Driven Development of Real-time Embedded Systems with Run-Time Monitoring and Animation via Highly Customizable Code Generation

This paper presents a vision that allows the combined use of model-driven engineering, run-time monitoring, and animation for the development and analysis of components in real-time embedded systems. Key building block in the tool environment supporting this vision is a highly-customizable code generation process. Customization is performed via a configuration specification which describes the ways in which input is provided to the component, the ways in which run-time execution information can be observed, and how these observations drive animation tools. The environment is envisioned to be suitable for different activities ranging from quality assurance to supporting certification, teaching, and outreach and will be built exclusively with open source tools to increase impact. A preliminary prototype implementation is described.

Remote operation of embedded controllers designed using IOPT Petri-nets

This paper presents a new communication architecture to enable the remote control, monitoring and debug of embedded-system controllers designed using IOPT Petri nets. IOPT Petri nets and the related tools (http://gres.uninova.pt) have been used as a rapid prototyping and development framework, including model-checking, simulation and automatic code generation tools. The new architecture adds remote operation capabilities to the controllers produced by the automatic code generators, enabling quasi-real-time remote debugging and monitoring using the IOPT simulator tool. Furthermore, it enables the creation of graphical user interfaces for remote operation and the development of distributed systems where a Petri net model running on a central system supervises the actions of multiple remote subsystems. © 2015 IEEE.

Generación automática de la configuración de subestaciones eléctricas según el Estándar IEC 61850 a partir de una herramienta de diseño gráfico

La evolución de las redes eléctricas se dirige hacia lo que se conoce como “Smart Grids” o “Redes Eléctricas Inteligentes”. Estas “Smart Grids” se componen de subestaciones eléctricas, que a su vez se componen de unos dispositivos llamados IEDs (Dispositivos Electrónicos Inteligentes – Intelligent Electronic Devices). El diseño de IEDs se encuentra definido en la norma IEC 61850, que especifica además un Lenguaje de Configuración de Subestaciones (Substation Configuration Language SCL) para la definición de la configuración de subestaciones y sus IEDs. Hoy en día, este estándar internacional no sólo se utiliza para diseñar correctamente IEDs y asegurar su interoperabilidad, sino que también se utiliza para el diseño de otros dispositivos de la red eléctrica, como por ejemplo, medidores inteligentes. Sin embargo, aunque existe una tendencia cada vez mayor del uso de este estándar, la comprensión y el manejo del mismo resulta difícil debido al gran volumen de información que lo compone y del nivel de detalle que utiliza, por lo que su uso para el diseño de IEDs se hace tedioso sin la ayuda de un soporte software. Es por ello que, para facilitar la aplicación del estándar IEC 61850 en el diseño de IEDs se han desarrollado herramientas como “Visual SCL”, “SCL Explorer” o “61850 SCLVisual Design Tool”. En concreto, “61850 SCLVisual Design Tool” es una herramienta gráfica para el modelado de subestaciones electricas, generada mediante el uso de los frameworks Eclipse Modeling Framework (EMF) y Epsilon Generative Modeling Technologies (GMT) y desarrollada por el grupo de investigación SYST de la UPM. El objetivo de este proyecto es añadir una nueva funcionalidad a la herramienta “61850 Visual SCL DesignTool”. Esta nueva funcionalidad consiste en la generación automática de un fichero de configuración de subestaciones eléctricas según el estándar IEC 61850 a partir de de una herramienta de diseño gráfico. Este fichero, se denomina SCD (Substation Configuration Description), y se trata de un fichero XML conforme a un esquema XSD (XML Schema Definition) mediante el que se define el lenguaje de configuración de subestaciones SCL del IEC 61850. Para el desarrollo de este proyecto, es necesario el estudio del lenguaje para la configuración de subestaciones SCL, así como del lenguaje gráfico específico de dominio definido por la herramienta “61850 SCLVisual Design Tool”, la estructura de los ficheros SCD, y finalmente, del lenguaje EGL (Epsilon Generation Language) para la transformación y generación automática de código a partir de modelos EMF. ABSTRACT Electrical networks are evolving to “Smart Grids”. Smart Grids are composed of electrical substations that in turn are composed of devices called IEDs (Intelligent Electronic Devices). The design of IEDs is defined by the IEC 61850 standard, which also specifies a Substation Configuration Languaje (SCL) used to define the configuration of substations and their IEDs. Nowadays, this international standard is not only used to design properly IEDs and guarantee their interoperability, but it is also used to design different electrical network devices, such as, smart meters. However, although the use of this standard is growing, its compression as well as its management, is still difficult due to its large volume of information and its level of detail. As a result, designing IEDs becomes a tedious task without a software support. As a consequence of this, in order to make easier the application of the IEC 61850 standard while designing IEDs, some software tools have been developed, such as: “Visual SCL”, “SCL Explorer” or “61850 SCLVisual Design Tool”. In particular, “61850 SCLVisual Design Tool” is a graphical tool used to make electrical substations models, and developed with the Eclipse Modeling Framework (EMF) and Epsilon Generative Modeling Technologies (GMT) by the research group SYST of the UPM. The aim of this project is to add a new functionality to “61850 Visual SCL DesignTool”. This new functionality consists of the automatic code generation of a substation configuration file according to the IEC 61850 standard. This file is called SCD (Substation Configuration Description), and it is a XML file that follows a XSD (XML Schema Definition) that defines the Substation Configuration Language (SCL) of the IEC 61850. In order to develop this project, it is necessary to study the Substation Configuration Language (SCL), the domain-specific graphical languaje defined by the tool “61850 SCLVisual Design Tool”, the structure of a SCD file, and the Epsilon Generation Language (EGL) used for the automatic code generation from EMF models

Three-dimensional modeling and highly refined mesh generation of the aorta artery and its tunics

This paper describes strategies and techniques to perform modeling and automatic mesh generation of the aorta artery and its tunics (adventitia, media and intima walls), using open source codes. The models were constructed in the Blender package and Python scripts were used to export the data necessary for the mesh generation in TetGen. The strategies proposed are able to provide meshes of complicated and irregular volumes, with a large number of mesh elements involved (12,000,000 tetrahedrons approximately). These meshes can be used to perform computational simulations by Finite Element Method (FEM). © Published under licence by IOP Publishing Ltd.

Generation of Testing Source Code for Object-Oriented Programs

Красимир Манев, Антон Желязков, Станимир Бойчев - В статията е представена имплементацията на последната фаза на автоматичен генератор на тестови данни за структурно тестване на софтуер, написан на обектно-ориентиран език за програмиране – генерирането на изходен код на тестващия модул. Някои детайли от имплементацията на останалите фази, които са важни за имплементацията на последната фаза, са представени първо. След това е описан и алгоритъмът за генериране на кода на тестващия модул.

Code Generator for Key Management Protocols - Design and Implementation

Key management has a fundamental role in secure communications. Designing and testing of key management protocols is tricky. These protocols must work flawlessly despite of any abuse. The main objective of this work was to design and implement a tool that helps to specify the protocol and makes it possible to test the protocol while it is still under development. This tool generates compile-ready java code from a key management protocol model. A modelling method for these protocols, which uses Unified Modeling Language (UML) was also developed. The protocol is modelled, exported as an XMI and read by the code generator tool. The code generator generates java code that is immediately executable with a test software after compilation.

Metodologia para modelagem, validação e programação de controladores lógicos industriais usando statecharts básicos

Due of industrial informatics several attempts have been done to develop notations and semantics, which are used for classifying and describing different kind of system behavior, particularly in the modeling phase. Such attempts provide the infrastructure to resolve some real problems of engineering and construct practical systems that aim at, mainly, to increase the productivity, quality, and security of the process. Despite the many studies that have attempted to develop friendly methods for industrial controller programming, they are still programmed by conventional trial-and-error methods and, in practice, there is little written documentation on these systems. The ideal solution would be to use a computational environment that allows industrial engineers to implement the system using high-level language and that follows international standards. Accordingly, this work proposes a methodology for plant and control modelling of the discrete event systems that include sequential, parallel and timed operations, using a formalism based on Statecharts, denominated Basic Statechart (BSC). The methodology also permits automatic procedures to validate and implement these systems. To validate our methodology, we presented two case studies with typical examples of the manufacturing sector. The first example shows a sequential control for a tagged machine, which is used to illustrated dependences between the devices of the plant. In the second example, we discuss more than one strategy for controlling a manufacturing cell. The model with no control has 72 states (distinct configurations) and, the model with sequential control generated 20 different states, but they only act in 8 distinct configurations. The model with parallel control generated 210 different states, but these 210 configurations act only in 26 distinct configurations, therefore, one strategy control less restrictive than previous. Lastly, we presented one example for highlight the modular characteristic of our methodology, which it is very important to maintenance of applications. In this example, the sensors for identifying pieces in the plant were removed. So, changes in the control model are needed to transmit the information of the input buffer sensor to the others positions of the cell

Geração automática de hardware a partir de especificações formais: estendendo uma abordagem de tradução

Removing inconsistencies in a project is a less expensive activity when done in the early steps of design. The use of formal methods improves the understanding of systems. They have various techniques such as formal specification and verification to identify these problems in the initial stages of a project. However, the transformation from a formal specification into a programming language is a non-trivial task and error prone, specially when done manually. The aid of tools at this stage can bring great benefits to the final product to be developed. This paper proposes the extension of a tool whose focus is the automatic translation of specifications written in CSPM into Handel-C. CSP is a formal description language suitable for concurrent systems, and CSPM is the notation used in tools support. Handel-C is a programming language whose result can be compiled directly into FPGA s. Our extension increases the number of CSPM operators accepted by the tool, allowing the user to define local processes, to rename channels in a process and to use Boolean guards on external choices. In addition, we also propose the implementation of a communication protocol that eliminates some restrictions on parallel composition of processes in the translation into Handel-C, allowing communication in a same channel between multiple processes to be mapped in a consistent manner and that improper communication in a channel does not ocurr in the generated code, ie, communications that are not allowed in the system specification

A development process proposal for the ERP5 system

Modeling ERP software means capturing the information necessary for supporting enterprise management. This modeling process goes down through different abstraction layers, from enterprise modeling to code generation. Thus ERP is the kind of system where enterprise engineering undoubtedly has, or should have, a strong influence. For the case of Free/Open Source ERP, the lack of proper modeling methods and tools can jeopardize the advantage brought by source code availability. Therefore, the aim of this paper is to present a development process proposal for the Open Source ERP5 system. The proposed development process aims to cover different abstraction levels, taking into account well established standards and common practices, as well as platform issues. Its main goal is to provide an adaptable meta-process to ERP5 adopters. © 2006 IEEE.

Adding Run-Time Monitoring to UML-RT by Modifying the Papyrus-RT Code Generator

In Model-Driven Engineering (MDE), the developer creates a model using a language such as Unified Modeling Language (UML) or UML for Real-Time (UML-RT) and uses tools such as Papyrus or Papyrus-RT that generate code for them based on the model they create. Tracing allows developers to get insights such as which events occur and timing information into their own application as it runs. We try to add monitoring capabilities using Linux Trace Toolkit: next generation (LTTng) to models created in UML-RT using Papyrus-RT. The implementation requires changing the code generator to add tracing statements for the events that the user wants to monitor to the generated code. We also change the makefile to automate the build process and we create an Extensible Markup Language (XML) file that allows developers to view their traces visually using Trace Compass, an Eclipse-based trace viewing tool. Finally, we validate our results using three models we create and trace.

A framework for table driven testing of Java classes

With the advent of object-oriented languages and the portability of Java, the development and use of class libraries has become widespread. Effective class reuse depends on class reliability which in turn depends on thorough testing. This paper describes a class testing approach based on modeling each test case with a tuple and then generating large numbers of tuples to thoroughly cover an input space with many interesting combinations of values. The testing approach is supported by the Roast framework for the testing of Java classes. Roast provides automated tuple generation based on boundary values, unit operations that support driver standardization, and test case templates used for code generation. Roast produces thorough, compact test drivers with low development and maintenance cost. The framework and tool support are illustrated on a number of non-trivial classes, including a graphical user interface policy manager. Quantitative results are presented to substantiate the practicality and effectiveness of the approach. Copyright (C) 2002 John Wiley Sons, Ltd.

Suporte a testes automáticos em aplicações web geradas com a OutSystems Platform

Dissertação de natureza científica para obtenção do grau de Mestre em Engenharia Informática e de Computadores

A Java expression evaluator for nonlinear programming

Finding the optimal value for a problem is usual in many areas of knowledge where in many cases it is needed to solve Nonlinear Optimization Problems. For some of those problems it is not possible to determine the expression for its objective function and/or its constraints, they are the result of experimental procedures, might be non-smooth, among other reasons. To solve such problems it was implemented an API contained methods to solve both constrained and unconstrained problems. This API was developed to be used either locally on the computer where the application is being executed or remotely on a server. To obtain the maximum flexibility both from the programmers’ and users’ points of view, problems can be defined as a Java class (because this API was developed in Java) or as a simple text input that is sent to the API. For this last one to be possible it was also implemented on the API an expression evaluator. One of the drawbacks of this expression evaluator is that it is slower than the Java native code. In this paper it is presented a solution that combines both options: the problem can be expressed at run-time as a string of chars that are converted to Java code, compiled and loaded dynamically. To wide the target audience of the API, this new expression evaluator is also compatible with the AMPL format.

CodeSkelGen: a program skeleton generator

Existent computer programming training environments help users to learn programming by solving problems from scratch. Nevertheless, initiating the resolution of a program can be frustrating and demotivating if the student does not know where and how to start. Skeleton programming facilitates a top-down design approach, where a partially functional system with complete high level structures is available, so the student needs only to progressively complete or update the code to meet the requirements of the problem. This paper presents CodeSkelGen - a program skeleton generator. CodeSkelGen generates skeleton or buggy Java programs from a complete annotated program solution provided by the teacher. The annotations are formally described within an annotation type and processed by an annotation processor. This processor is responsible for a set of actions ranging from the creation of dummy methods to the exchange of operator types included in the source code. The generator tool will be included in a learning environment that aims to assist teachers in the creation of programming exercises and to help students in their resolution.