Melt-compounded nanocomposites of titanium dioxide atomic-layer-deposition-coated polyamide and polystyrene powders

Polyamide and polystyrene particles were coated with titanium dioxide films by atomic layer deposition (ALD) and then melt-compounded to form polymer nanocomposites. The rheological properties of the ALD-created nanocomposite materials were characterized with a melt flow indexer, a melt flow spiral mould, and a rotational rheometer. The results suggest that the melt flow properties of polyamide nanocomposites were markedly better than those of pure polyamide and polystyrene nanocomposites. Such behavior was shown to originate in an uncontrollable decrease in the polyamide molecular weight, likely affected by a high thin-film impurity content, as shown in gel permeation chromatography (GPC) and scanning electron microscope (SEM) equipped with an energy-dispersive spectrometer. Transmission electron microscope image showed that a thin film grew on both studied polymer particles, and that subsequent melt-compounding was successful, producing well dispersed ribbon-like titanium dioxide with the titanium dioxide filler content ranging from 0.06 to 1.12wt%. Even though we used nanofillers with a high aspect ratio, they had only a minor effect on the tensile and flexural properties of the polystyrene nanocomposites. The mechanical behavior of polyamide nanocomposites was more complex because of the molecular weight degradation. Our approach here to form polymeric nanocomposites is one way to tailor ceramic nanofillers and form homogenous polymer nanocomposites with minimal work-related risks in handling powder form nanofillers. However, further research is needed to gauge the commercial potential of ALD-created nanocomposite materials. Copyright (C) 2011 John Wiley & Sons, Ltd.

Preparation and Characterization ofHigh-k Aluminum Oxide Thin Films by Atomic Layer Deposition for Gate Dielectric Applications

Present work deals with the Preparation and characterization of high-k aluminum oxide thin films by atomic layer deposition for gate dielectric applications.The ever-increasing demand for functionality and speed for semiconductor applications requires enhanced performance, which is achieved by the continuous miniaturization of CMOS dimensions. Because of this miniaturization, several parameters, such as the dielectric thickness, come within reach of their physical limit. As the required oxide thickness approaches the sub- l nm range, SiO 2 become unsuitable as a gate dielectric because its limited physical thickness results in excessive leakage current through the gate stack, affecting the long-term reliability of the device. This leakage issue is solved in the 45 mn technology node by the integration of high-k based gate dielectrics, as their higher k-value allows a physically thicker layer while targeting the same capacitance and Equivalent Oxide Thickness (EOT). Moreover, Intel announced that Atomic Layer Deposition (ALD) would be applied to grow these materials on the Si substrate. ALD is based on the sequential use of self-limiting surface reactions of a metallic and oxidizing precursor. This self-limiting feature allows control of material growth and properties at the atomic level, which makes ALD well-suited for the deposition of highly uniform and conformal layers in CMOS devices, even if these have challenging 3D topologies with high aspect-ratios. ALD has currently acquired the status of state-of-the-art and most preferred deposition technique, for producing nano layers of various materials of technological importance. This technique can be adapted to different situations where precision in thickness and perfection in structures are required, especially in the microelectronic scenario.

Effect of reaction mechanism on precursor exposure time in atomic layer deposition of silicon oxide and silicon nitride

Atomic layer deposition (ALD) of highly conformal, silicon-based dielectric thin films has become necessary because of the continuing decrease in feature size in microelectronic devices. The ALD of oxides and nitrides is usually thought to be mechanistically similar, but plasma-enhanced ALD of silicon nitride is found to be problematic, while that of silicon oxide is straightforward. To find why, the ALD of silicon nitride and silicon oxide dielectric films was studied by applying ab initio methods to theoretical models for proposed surface reaction mechanisms. The thermodynamic energies for the elimination of functional groups from different silicon precursors reacting with simple model molecules were calculated using density functional theory (DFT), explaining the lower reactivity of precursors toward the deposition of silicon nitride relative to silicon oxide seen in experiments, but not explaining the trends between precursors. Using more realistic cluster models of amine and hydroxyl covered surfaces, the structures and energies were calculated of reaction pathways for chemisorption of different silicon precursors via functional group elimination, with more success. DFT calculations identified the initial physisorption step as crucial toward deposition and this step was thus used to predict the ALD reactivity of a range of amino-silane precursors, yielding good agreement with experiment. The retention of hydrogen within silicon nitride films but not in silicon oxide observed in FTIR spectra was accounted for by the theoretical calculations and helped verify the application of the model.

Adsorption Calorimetry for Energy Conversion Technologies: Applications in Organic Photovoltaics, Catalysis, and Atomic Layer Deposition

Thesis (Ph.D.)--University of Washington, 2016-07

Investigating routes toward atomic layer deposition of silicon carbide: Ab initio screening of potential silicon and carbon precursors

Silicon carbide (SiC) is a promising material for electronics due to its hardness, and ability to carry high currents and high operating temperature. SiC films are currently deposited using chemical vapor deposition (CVD) at high temperatures 1500–1600 °C. However, there is a need to deposit SiC-based films on the surface of high aspect ratio features at low temperatures. One of the most precise thin film deposition techniques on high-aspect-ratio surfaces that operates at low temperatures is atomic layer deposition (ALD). However, there are currently no known methods for ALD of SiC. Herein, the authors present a first-principles thermodynamic analysis so as to screen different precursor combinations for SiC thin films. The authors do this by calculating the Gibbs energy ΔGΔG of the reaction using density functional theory and including the effects of pressure and temperature. This theoretical model was validated for existing chemical reactions in CVD of SiC at 1000 °C. The precursors disilane (Si2H6), silane (SiH4), or monochlorosilane (SiH3Cl) with ethyne (C2H2), carbontetrachloride (CCl4), or trichloromethane (CHCl3) were predicted to be the most promising for ALD of SiC at 400 °C.

Kinetics and coverage dependent reaction mechanisms of the copper atomic layer deposition from copper dimethylamino-2-propoxide and diethylzinc

Atomic layer deposition (ALD) has been recognized as a promising method to deposit conformal and uniform thin film of copper for future electronic devices. However, many aspects of the reaction mechanism and the surface chemistry of copper ALD remain unclear. In this paper, we employ plane wave density functional theory (DFT) to study the transmetalation ALD reaction of copper dimethylamino-2-propoxide [Cu(dmap)2] and diethylzinc [Et2Zn] that was realized experimentally by Lee et al. [ Angew. Chem., Int. Ed. 2009, 48, 4536−4539]. We find that the Cu(dmap)2 molecule adsorbs and dissociates through the scission of one or two Cu–O bonds into surface-bound dmap and Cu(dmap) fragments during the copper pulse. As Et2Zn adsorbs on the surface covered with Cu(dmap) and dmap fragments, butane formation and desorption was found to be facilitated by the surrounding ligands, which leads to one reaction mechanism, while the migration of ethyl groups to the surface leads to another reaction mechanism. During both reaction mechanisms, ligand diffusion and reordering are generally endothermic processes, which may result in residual ligands blocking the surface sites at the end of the Et2Zn pulse, and in residual Zn being reduced and incorporated as an impurity. We also find that the nearby ligands play a cooperative role in lowering the activation energy for formation and desorption of byproducts, which explains the advantage of using organometallic precursors and reducing agents in Cu ALD. The ALD growth rate estimated for the mechanism is consistent with the experimental value of 0.2 Å/cycle. The proposed reaction mechanisms provide insight into ALD processes for copper and other transition metals.

Nano-Engineering of Densely Packed Electrochemical Energy Storage Architectures by Atomic Layer Deposition

Nanostructures are highly attractive for future electrical energy storage devices because they enable large surface area and short ion transport time through thin electrode layers for high power devices. Significant enhancement in power density of batteries has been achieved by nano-engineered structures, particularly anode and cathode nanostructures spatially separated far apart by a porous membrane and/or a defined electrolyte region. A self-aligned nanostructured battery fully confined within a single nanopore presents a powerful platform to determine the rate performance and cyclability limits of nanostructured storage devices. Atomic layer deposition (ALD) has enabled us to create and evaluate such structures, comprised of nanotubular electrodes and electrolyte confined within anodic aluminum oxide (AAO) nanopores. The V2O5- V2O5 symmetric nanopore battery displays exceptional power-energy performance and cyclability when tested as a massively parallel device (~2billion/cm2), each with ~1m3 volume (~1fL). Cycled between 0.2V and 1.8V, this full cell has capacity retention of 95% at 5C rate and 46% at 150C, with more than 1000 charge/discharge cycles. These results demonstrate the promise of ultrasmall, self-aligned/regular, densely packed nanobattery structures as a testbed to study ionics and electrodics at the nanoscale with various geometrical modifications and as a building block for high performance energy storage systems[1, 2]. Further increase of full cell output potential is also demonstrated in asymmetric full cell configurations with various low voltage anode materials. The asymmetric full cell nanopore batteries, comprised of V2O5 as cathode and prelithiated SnO2 or anatase phase TiO2 as anode, with integrated nanotubular metal current collectors underneath each nanotubular storage electrode, also enabled by ALD. By controlling the amount of lithium ion prelithiated into SnO2 anode, we can tune full cell output voltage in the range of 0.3V and 3V. This asymmetric nanopore battery array displays exceptional rate performance and cyclability. When cycled between 1V and 3V, it has capacity retention of approximately 73% at 200C rate compared to 1C, with only 2% capacity loss after more than 500 charge/discharge cycles. With increased full cell output potential, the asymmetric V2O5-SnO2 nanopore battery shows significantly improved energy and power density. This configuration presents a more realistic test - through its asymmetric (vs symmetric) configuration – of performance and cyclability in nanoconfined environment. This dissertation covers (1) Ultra small electrochemical storage platform design and fabrication, (2) Electron and ion transport in nanostructured electrodes inside a half cell configuration, (3) Ion transport between anode and cathode in confined nanochannels in symmetric full cells, (4) Scale up energy and power density with geometry optimization and low voltage anode materials in asymmetric full cell configurations. As a supplement, selective growth of ALD to improve graphene conductance will also be discussed[3]. References: 1. Liu, C., et al., (Invited) A Rational Design for Batteries at Nanoscale by Atomic Layer Deposition. ECS Transactions, 2015. 69(7): p. 23-30. 2. Liu, C.Y., et al., An all-in-one nanopore battery array. Nature Nanotechnology, 2014. 9(12): p. 1031-1039. 3. Liu, C., et al., Improving Graphene Conductivity through Selective Atomic Layer Deposition. ECS Transactions, 2015. 69(7): p. 133-138.

Copper Diffusion Barrier Deposition on Integrated Circuit Devices by Atomic Layer Deposition Technique

Transfer from aluminum to copper metallization and decreasing feature size of integrated circuit devices generated a need for new diffusion barrier process. Copper metallization comprised entirely new process flow with new materials such as low-k insulators and etch stoppers, which made the diffusion barrier integration demanding. Atomic Layer Deposition technique was seen as one of the most promising techniques to deposit copper diffusion barrier for future devices. Atomic Layer Deposition technique was utilized to deposit titanium nitride, tungsten nitride, and tungsten nitride carbide diffusion barriers. Titanium nitride was deposited with a conventional process, and also with new in situ reduction process where titanium metal was used as a reducing agent. Tungsten nitride was deposited with a well-known process from tungsten hexafluoride and ammonia, but tungsten nitride carbide as a new material required a new process chemistry. In addition to material properties, the process integration for the copper metallization was studied making compatibility experiments on different surface materials. Based on these studies, titanium nitride and tungsten nitride processes were found to be incompatible with copper metal. However, tungsten nitride carbide film was compatible with copper and exhibited the most promising properties to be integrated for the copper metallization scheme. The process scale-up on 300 mm wafer comprised extensive film uniformity studies, which improved understanding of non-uniformity sources of the ALD growth and the process-specific requirements for the ALD reactor design. Based on these studies, it was discovered that the TiN process from titanium tetrachloride and ammonia required the reactor design of perpendicular flow for successful scale-up. The copper metallization scheme also includes process steps of the copper oxide reduction prior to the barrier deposition and the copper seed deposition prior to the copper metal deposition. Easy and simple copper oxide reduction process was developed, where the substrate was exposed gaseous reducing agent under vacuum and at elevated temperature. Because the reduction was observed efficient enough to reduce thick copper oxide film, the process was considered also as an alternative method to make the copper seed film via copper oxide reduction.

Atomic layer deposition of ZrO2 thin films: Study of growth kinetics and dielectric behaviour

Thin films of ZrO2 have been deposited by ALD on Si(100) and SIMOX using two different metalorganic complexes of Zr as precursors. These films are characterized by X-ray diffraction, transmission and scanning electron microscopies, infrared spectroscopy, and electrical measurements. These show that amorphous ZrO2 films of high dielectric quality may be grown on Si(100) starting about 400degreesC. As the growth temperature is raised, the films become crystalline, the phase formed and the microstructure depending on precursor molecular structure. The phase of ZrO2 formed depends also on the relative duration of the precursor and oxygen pulses. XPS and IR spectroscopy show that films grown at low temperatures contain chemically unbound carbon, its extent depending on the precursor. C-V measurements show that films grown on Si(100) have low interface state density, low leakage current, a hysteresis width of only 10-250 mV and a dielectric constant of similar to16-25.

Atomic layer deposition of interface control layers for the fabrication of III/V MOS devices

The continued advancement of metal oxide semiconductor field effect transistor (MOSFET) technology has shifted the focus from Si/SiO2 transistors towards high-κ/III-V transistors for high performance, faster devices. This has been necessary due to the limitations associated with the scaling of the SiO2 thickness below ~1 nm and the associated increased leakage current due to direct electron tunnelling through the gate oxide. The use of these materials exhibiting lower effective charge carrier mass in conjunction with the use of a high-κ gate oxide allows for the continuation of device scaling and increases in the associated MOSFET device performance. The high-κ/III-V interface is a critical challenge to the integration of high-κ dielectrics on III-V channels. The interfacial chemistry of the high-κ/III-V system is more complex than Si, due to the nature of the multitude of potential native oxide chemistries at the surface with the resultant interfacial layer showing poor electrical insulating properties when high-κ dielectrics are deposited directly on these oxides. It is necessary to ensure that a good quality interface is formed in order to reduce leakage and interface state defect density to maximise channel mobility and reduce variability and power dissipation. In this work, the ALD growth of aluminium oxide (Al2O3) and hafnium oxide (HfO2) after various surface pre-treatments was carried out, with the aim of improving the high-κ/III-V interface by reducing the Dit – the density of interface defects caused by imperfections such as dangling bonds, dimers and other unsatisfied bonds at the interfaces of materials. A brief investigation was performed into the structural and electrical properties of Al2O3 films deposited on In0.53Ga0.47As at 200 and 300oC via a novel amidinate precursor. Samples were determined to experience a severe nucleation delay when deposited directly on native oxides, leading to diminished functionality as a gate insulator due to largely reduced growth per cycle. Aluminium oxide MOS capacitors were prepared by ALD and the electrical characteristics of GaAs, In0.53Ga0.47As and InP capacitors which had been exposed to pre-pulse treatments from triethyl gallium and trimethyl indium were examined, to determine if self-cleaning reactions similar to those of trimethyl aluminium occur for other alkyl precursors. An improved C-V characteristic was observed for GaAs devices indicating an improved interface possibly indicating an improvement of the surface upon pre-pulsing with TEG, conversely degraded electrical characteristics observed for In0.53Ga0.47As and InP MOS devices after pre-treatment with triethyl gallium and trimethyl indium respectively. The electrical characteristics of Al2O3/In0.53Ga0.47As MOS capacitors after in-situ H2/Ar plasma treatment or in-situ ammonium sulphide passivation were investigated and estimates of interface Dit calculated. The use of plasma reduced the amount of interface defects as evidenced in the improved C-V characteristics. Samples treated with ammonium sulphide in the ALD chamber were found to display no significant improvement of the high-κ/III-V interface. HfO2 MOS capacitors were fabricated using two different precursors comparing the industry standard hafnium chloride process with deposition from amide precursors incorporating a ~1nm interface control layer of aluminium oxide and the structural and electrical properties investigated. Capacitors furnished from the chloride process exhibited lower hysteresis and improved C-V characteristics as compared to that of hafnium dioxide grown from an amide precursor, an indication that no etching of the film takes place using the chloride precursor in conjunction with a 1nm interlayer. Optimisation of the amide process was carried out and scaled samples electrically characterised in order to determine if reduced bilayer structures display improved electrical characteristics. Samples were determined to exhibit good electrical characteristics with a low midgap Dit indicative of an unpinned Fermi level