A high-power-factor, three-phase isolated AC-DC converter using high-frequency current injection

A single-stage, three-phase AC-to-DC converter topology is proposed for high-frequency power supply applications. The principal features of the circuit include continuous current operation of the three AC input inductors, inherent shaping of the input currents, resulting in high power factor, a transformer isolated output, and only two active devices are required, both soft-switched. Resonant conversion techniques are used, and a high power factor is achieved by injecting high-frequency currents into the three-phase rectifier, producing a high frequency modulation of the rectifier input voltages. The current injection principle is explained and the system operation is confirmed by a combination of simulation and experimental results.

Analysis of voltage source converter-based high-voltage direct current under DC line-to-earth fault

DC line faults on high-voltage direct current (HVDC) systems utilising voltage source converters (VSCs) are a major issue for multi-terminal HVDC systems in which complete isolation of the faulted system is not a viable option. Of these faults, single line-to-earth faults are the most common fault scenario. To better understand the system under such faults, this study analyses the behaviour of HVDC systems based on both conventional two-level converter and multilevel modular converter technology, experiencing a permanent line-to-earth fault. Operation of the proposed system under two different earthing configurations of converter side AC transformer earthed with converter unearthed, and both converter and AC transformer unearthed, was analysed and simulated, with particular attention paid to the converter operation. It was observed that the development of potential earth loops within the system as a result of DC line-to-earth faults leads to substantial overcurrent and results in oscillations depending on the earthing configuration.

Uma aplicacao da celula de comutacao ZVS-PWM-GEPAE ao conversor DC-AC

This work presents the design and procedure of a DC-to-AC converter using a ZVS Commutation Cell developed by Barbi and Martins (1991) and applied to the family of DC-to-DC PWM converters. Firstly, we show the cell applied to buck converter. The stages of operation and the main current and voltage equations of the resonant devices are presented. Next, we adapt the converter to the regenerative operation mode. Hence, the full bridge converter at low frequency operation is conected on the DC-to-DC stage (at high frequency) output ends (Seixas, 1993). Commutation of zero voltage for all switches, PWM at constant frequency and neither overvoltage nor additional current stress are observed by digital simulation. The design example and experimental results obtained by prototype rated at 275 V, 1 kW and 40 kHz are also presented.

Trolleybus power system for operation with AC or DC distribution networks

This paper presents the development and experimental analysis of a special input stage converter for a Trolleybus type vehicle allowing its operation in AC (two wires, single-phase) or DC distribution networks. The architecture of proposed input stage converter is composed by five interleaved boost rectifiers operating in discontinuous conduction mode. Furthermore, due to the power lines characteristics, the proposed input power structure can act as AC to DC or as DC to DC converter providing a proper DC output voltage range required to the DC bus. When operation is AC to DC, the converter is capable to provide high power factor with reduced harmonic distortion for the input current, complying with the restrictions imposed by IEC 61000-3-4 standard. Finally, the main experimental results are presented in order to verify the feasibility of the proposed converter, demonstrating the benefits and the possibility for AC feeding system for trolleybus type vehicle. © 2010 IEEE.

High efficiency SiC AC chopper for LV networks

A proposal to increase the existing residential LV grid voltage from 230 V has been made in order to increase existing network capacity. A power-electronic AC-AC converter is then used to provide 230 V at each property. Several constraints such as temperature rise at the converter location lead to a converter design requiring very high efficiency. In this paper results from a recent feasibility study in terms of LV network capacity increase are presented along with the design and testing of a SiC based 1 kW, AC/AC prototype module, which forms the basis of a much larger 15 kW multi-module converter.

Cascaded DC-DC converter connection of photovoltaic modules

New residential scale photovoltaic (PV) arrays are commonly connected to the grid by a single dc-ac inverter connected to a series string of pv panels, or many small dc-ac inverters which connect one or two panels directly to the ac grid. This paper proposes an alternative topology of nonisolated per-panel dc-dc converters connected in series to create a high voltage string connected to a simplified dc-ac inverter. This offers the advantages of a "converter-per-panel" approach without the cost or efficiency penalties of individual dc-ac grid connected inverters. Buck, boost, buck-boost, and Cu´k converters are considered as possible dc-dc converters that can be cascaded. Matlab simulations are used to compare the efficiency of each topology as well as evaluating the benefits of increasing cost and complexity. The buck and then boost converters are shown to be the most efficient topologies for a given cost, with the buck best suited for long strings and the boost for short strings. While flexible in voltage ranges, buck-boost, and Cu´k converters are always at an efficiency or alternatively cost disadvantage.

Electronic load interface for improving PV dual-converter system operational margin

An electronic load interface (ELI) for improving the operational margin of a photovoltaic (PV) dual-converter system under dynamic conditions is presented. The ELI - based on a modified buck-boost converter - interfaces the output of the converters and the load system. It improves the operational margin of the PV dual-converter system by extending the conditions under which the dual-converter system operates at the maximum power point. The ELI is activated as and when needed, so as minimise system losses. By employing the ELI, utilisation and efficiency of a PV dual-converter system increases. In general, the concept of the ELI can be applied to multi-converter PV systems - such as multi-converter inverters, and multi-converter DC-DC converter systems - for performance and efficiency improvement. © 2013 The Institution of Engineering and Technology.

A 10-bit 2GHz current-steering CMOS D/A converter

This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply.

Dual-polarization multi-band optical OFDM transmission and transceiver limitations for up to 500 Gb/s uncompensated long-haul links

A number of critical issues for dual-polarization single- and multi-band optical orthogonal-frequency division multiplexing (DPSB/ MB-OFDM) signals are analyzed in dispersion compensation fiber (DCF)-free long-haul links. For the first time, different DP crosstalk removal techniques are compared, the maximum transmission-reach is investigated, and the impact of subcarrier number and high-level modulation formats are explored thoroughly. It is shown, for a bit-error-rate (BER) of 10-3, 2000 km of quaternary phase-shift keying (QPSK) DP-MBOFDM transmission is feasible. At high launched optical powers (LOP), maximum-likelihood decoding can extend the LOP of 40 Gb/s QPSK DPSB- OFDM at 2000 km by 1.5 dB compared to zero-forcing. For a 100 Gb/s DP-MB-OFDM system, a high number of subcarriers contribute to improved BER but at the cost of digital signal processing computational complexity, whilst by adapting the cyclic prefix length the BER can be improved for a low number of subcarriers. In addition, when 16-quadrature amplitude modulation (16QAM) is employed the digital-toanalogue/ analogue-to-digital converter (DAC/ADC) bandwidth is relaxed with a degraded BER; while the 'circular' 8QAM is slightly superior to its 'rectangular' form. Finally, the transmission of wavelength-division multiplexing DP-MB-OFDM and single-carrier DP-QPSK is experimentally compared for up to 500 Gb/s showing great potential and similar performance at 1000 km DCF-free G.652 line. © 2014 Optical Society of America.

Remediation strategies of shaft and common mode voltages in adjustable speed drive systems

AC motors are largely used in a wide range of modern systems, from household appliances to automated industry applications such as: ventilations systems, fans, pumps, conveyors and machine tool drives. Inverters are widely used in industrial and commercial applications due to the growing need for speed control in ASD systems. Fast switching transients and the common mode voltage, in interaction with parasitic capacitive couplings, may cause many unwanted problems in the ASD applications. These include shaft voltage and leakage currents. One of the inherent characteristics of Pulse Width Modulation (PWM) techniques is the generation of the common mode voltage, which is defined as the voltage between the electrical neutral of the inverter output and the ground. Shaft voltage can cause bearing currents when it exceeds the amount of breakdown voltage level of the thin lubricant film between the inner and outer rings of the bearing. This phenomenon is the main reason for early bearing failures. A rapid development in power switches technology has lead to a drastic decrement of switching rise and fall times. Because there is considerable capacitance between the stator windings and the frame, there can be a significant capacitive current (ground current escaping to earth through stray capacitors inside a motor) if the common mode voltage has high frequency components. This current leads to noises and Electromagnetic Interferences (EMI) issues in motor drive systems. These problems have been dealt with using a variety of methods which have been reported in the literature. However, cost and maintenance issues have prevented these methods from being widely accepted. Extra cost or rating of the inverter switches is usually the price to pay for such approaches. Thus, the determination of cost-effective techniques for shaft and common mode voltage reduction in ASD systems, with the focus on the first step of the design process, is the targeted scope of this thesis. An introduction to this research – including a description of the research problem, the literature review and an account of the research progress linking the research papers – is presented in Chapter 1. Electrical power generation from renewable energy sources, such as wind energy systems, has become a crucial issue because of environmental problems and a predicted future shortage of traditional energy sources. Thus, Chapter 2 focuses on the shaft voltage analysis of stator-fed induction generators (IG) and Doubly Fed Induction Generators DFIGs in wind turbine applications. This shaft voltage analysis includes: topologies, high frequency modelling, calculation and mitigation techniques. A back-to-back AC-DC-AC converter is investigated in terms of shaft voltage generation in a DFIG. Different topologies of LC filter placement are analysed in an effort to eliminate the shaft voltage. Different capacitive couplings exist in the motor/generator structure and any change in design parameters affects the capacitive couplings. Thus, an appropriate design for AC motors should lead to the smallest possible shaft voltage. Calculation of the shaft voltage based on different capacitive couplings, and an investigation of the effects of different design parameters are discussed in Chapter 3. This is achieved through 2-D and 3-D finite element simulation and experimental analysis. End-winding parameters of the motor are also effective factors in the calculation of the shaft voltage and have not been taken into account in previous reported studies. Calculation of the end-winding capacitances is rather complex because of the diversity of end winding shapes and the complexity of their geometry. A comprehensive analysis of these capacitances has been carried out with 3-D finite element simulations and experimental studies to determine their effective design parameters. These are documented in Chapter 4. Results of this analysis show that, by choosing appropriate design parameters, it is possible to decrease the shaft voltage and resultant bearing current in the primary stage of generator/motor design without using any additional active and passive filter-based techniques. The common mode voltage is defined by a switching pattern and, by using the appropriate pattern; the common mode voltage level can be controlled. Therefore, any PWM pattern which eliminates or minimizes the common mode voltage will be an effective shaft voltage reduction technique. Thus, common mode voltage reduction of a three-phase AC motor supplied with a single-phase diode rectifier is the focus of Chapter 5. The proposed strategy is mainly based on proper utilization of the zero vectors. Multilevel inverters are also used in ASD systems which have more voltage levels and switching states, and can provide more possibilities to reduce common mode voltage. A description of common mode voltage of multilevel inverters is investigated in Chapter 6. Chapter 7 investigates the elimination techniques of the shaft voltage in a DFIG based on the methods presented in the literature by the use of simulation results. However, it could be shown that every solution to reduce the shaft voltage in DFIG systems has its own characteristics, and these have to be taken into account in determining the most effective strategy. Calculation of the capacitive coupling and electric fields between the outer and inner races and the balls at different motor speeds in symmetrical and asymmetrical shaft and balls positions is discussed in Chapter 8. The analysis is carried out using finite element simulations to determine the conditions which will increase the probability of high rates of bearing failure due to current discharges through the balls and races.

The gated integration technique for the accurate measurement of the autocorrelation function of speckle intensities scattered from random phase screens

A new approach based on the gated integration technique is proposed for the accurate measurement of the autocorrelation function of speckle intensities scattered from a random phase screen. The Boxcar used for this technique in the acquisition of the speckle intensity data integrates the photoelectric signal during its sampling gate open, and it repeats the sampling by a preset number, in. The average analog of the in samplings output by the Boxcar enhances the signal-to-noise ratio by root m, because the repeated sampling and the average make the useful speckle signals stable, while the randomly varied photoelectric noise is suppressed by 1/ root m. In the experiment, we use an analog-to-digital converter module to synchronize all the actions such as the stepped movement of the phase screen, the repeated sampling, the readout of the averaged output of the Boxcar, etc. The experimental results show that speckle signals are better recovered from contaminated signals, and the autocorrelation function with the secondary maximum is obtained, indicating that the accuracy of the measurement of the autocorrelation function is greatly improved by the gated integration technique. (C) 2006 Elsevier Ltd. All rights reserved.

On-line topographic analysis in the SEM

A novel method for on-line topographic analysis of rough surfaces in the SEM has been investigated. It utilises a digital minicomputer configured to act as a programmable scan generator and automatic focusing unit. The computer is coupled to the microscope through digital-to-analogue converters which enable it to generate ramp waveforms allowing the beam to be scanned over a small sub-region of the field under program control. A further digital-to-analogue converter regulates the current supply to the objective lens of the microscope. The video signal is sampled by means of an analogue-to-digital converter and the resultant binary code stored in the computer's memory as an array of numbers describing relative image intensity. Computations based on the intensity gradient of the image allow the objective lens current to be found for the in-focus condition, which may be related to the working distance through a previous calibration experiment. The sensitivity of the method for detecting small height changes is theoretically of the order of 1 μm. In practice the operator specifies features of interest by means of a mobile spot cursor injected into the SEM display screen, or he may scan the specimen at sub-regions corresponding to pre-determined points on a regular grid defined by him. The operation then proceeds under program control. | A novel method for on-line topographic analysis of rough surfaces in the SEM has been investigated. It utilizes a digital minicomputer configured to act as a programmable scan generator and automatic focusing unit. A further digital-to-analog converter regulates the current supply to the objective lens of the microscope. The video signal is sampled by means of an analog-to-digital converter and the resultant binary code stored in the computer's memory as an array of numbers describing relative image intensity. The sensitivity of the method for detecting small height changes is theroretically of the order of 1 mu m.

Topographical analysis in the SEM using an automatic focusing technique

A novel technique for automated topographical analysis in the SEM has been investigated. It utilizes a 16-bit minicomputer arranged to act as an automatic focusing unit. The computer is coupled to the objective lens of the microscope, by means of a digital to analogue converter, and may regulate the excitation of the lens under program control. Further digital-to-analogue converters allow the computer to act as a programmable scan generator by applying ramp waveforms to the scan amplifiers, permitting the beam to be swept over a small sub-region of the field of interest. The video signal is sampled and applied to an analogue-to-digital converter; the resultant binary numbers are stored in computer memory as an array of values representing relative image intensities within a subregion. A differencing algorithm applied to the collected data allows the level of objective lens excitation to be found at which the sharpness of the image is optimized, and the excitation may be related to the working distance for that subregion through a previous calibration experiment. The sensitivity of the method for detecting small height changes is theoretically of the order of 1 μm.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

An 8-b 1-GSmaples/s CMOS cascaded folding and interpolating ADC

This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC. The circuit including a bandgap is implemented in a 0.18-mu m CMOS technology, and measures 1.47 mm X 1.47 mm (including pads). The simulation results illustrate a conversion rate of 1-GSamples/s and a power dissipation of less than 290mW.