Simulation of surface and volume stress for high voltage transmission insulators

The bulk of power transmission from the generating stations to the load centres is carried through overhead lines. The distances involved could span several hundreds of kilometres. To minimize line losses, power transmission over such long distances is carried out at high voltages (several hundreds of kV). A network of outdoor lines operating at different voltages has been found to be the most economical method of power delivery. The disc insulators perform dual task of mechanically supporting and electrically isolating the live phase conductors from the support tower. These insulators have to perform under various environmental conditions; hence the electrical stress distribution along the insulators governs the possible flashover, which is quite detrimental to the system. In view of this the present investigation aims to simulate the surface electric field stress on different types of porcelain/ceramic insulators; both normal and anti-fog type discs which are used for high voltage transmission/distribution systems are considered. The surface charge simulation method is employed for the field computation to simulate potential, electric field, surface and bulk/volume stress.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Analysis of current voltage characteristics of MWIR homojunction photodiodes for uncooled operation

Dark currents n(+)/v/p(+) Hg0.69Cd0.Te-31 mid wave infrared photodiodes were measured at room temperature. The diodes exhibited negative differential resistance at room-temperature, but with increasing leakage currents as a function of reverse bias. The current-voltage characteristics were simulated and fitted by incorporating trap assisted tunneling via traps and Shockley-Read-Hall generation recombination process due to dislocations in the carrier transport equations. The thermal suppression of carriers was simulated by taking energy level of trap (E-t), trap density (N-t) and the doping concentrations of n(+) and v regions as fitting parameters. Values of E-t and N-t were 0.78E(g) and similar to 6-9 x 10(14) cm(-3) respectively for most of the diodes. Variable temperature current voltage measurements on variable area diode array (VADA) structures confirmed the fact that variation in zero bias resistance area product (R(0)A) is related to g-r processes originating from variation in concentration and kind of defects that intersect a junction area. (C) 2012 Elsevier B.V. All rights reserved.

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V th) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φ c) saturates to Φ c (s a t), and analyze the effects of oxide thickness (t ox) and substrate doping (N A) variations on V th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V t h definition, electrically corresponds to a condition where the inversion layer capacitance (C i n v) is equal to the oxide capacitance (C o x) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C i n v C o x is proposed to compute Φ c (s a t), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (x) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film. © 2012 American Institute of Physics.

Analysis of the temperature-dependent current-voltage characteristics and the barrier-height inhomogeneities of Au/GaN Schottky diodes

In this report, the currentvoltage (IV) characteristics of Au/GaN Schottky diodes have been carried out in the temperature range of 300510?K. The estimated values of the Schottky-barrier height (SBH) and the ideality factor of the diodes based on the thermionic emission (TE) mechanism were found to be temperature dependent. The barrier height was found to increase and the ideality factor to decrease with increasing temperature. The conventional Richardson plot of ln(Is/T2) versus 1/kT gives the SBH of 0.51?eV and Richardson constant value of 3.23?X?10-5?A?cm-2?K-2 which is much lower than the known value of 26.4?A?cm-2?K-2 for GaN. Such discrepancies of the SBH and Richardson constant value were attributed to the existence of barrier-height inhomogeneities at the Au/GaN interface. The modified Richardson plot of ln(Is/T2)q2 sigma 2/2k2T2 versus q/kT, by assuming a Gaussian distribution of barrier heights at the Au/GaN interface, provided the SBH of 1.47?eV and Richardson constant value of 38.8?A?cm-2?K-2. The temperature dependence of the barrier height is interpreted on the basis of existence of the Gaussian distribution of the barrier heights due to the barrier-height inhomogeneities at the Au/GaN interface.

Development of moving magnet type linear motor for dual piston compressor for pulse tube cryocooler

This paper describes the design, fabrication and testing of a moving magnet type linear motor of dual piston configuration for a pulse tube cryocooler for ground applications. Eight radially magnetized segmented magnets were used to form one set of a magnet ring. Four magnet rings of such type were constructed, in which one pair of rings has north-pole on its outer diameter and south-pole on inner diameter, while the other pair is it's complementary. The magnets were mounted with opposite poles together on the magnet holder with an axial moving shaft having a piston mounted on both ends of the shaft. The shaft movement was restricted to the axial direction by using C-clamp type flexures, mounted on both sides of the shaft. The force requirement for driving the compressor was calculated based on which the electrical circuit of motor is designed by proper selection of wire gauge and Ampere-turns. The flexure spring force estimation was done through simulation using ANSYS 11.0 and was verified experimentally; while the magnet spring force was determined experimentally. The motor with mounted piston was tested using a variable voltage and variable frequency power supply capable of driving 140 watts of load.

Distinct Disulfide Isomers of mu-Conotoxins KIIIA and KIIIB Block Voltage-Gated Sodium Channels

In the preparation of synthetic conotoxins containing multiple disulfide bonds, oxidative folding can produce numerous permutations of disulfide bond connectivities. Establishing the native disulfide connectivities thus presents a significant challenge when the venom-derived peptide is not available, as is increasingly the case when conotoxins are identified from cDNA sequences. Here, we investigate the disulfide connectivity of mu-conotoxin KIIIA, which was predicted originally to have a C1-C9,C2-C15,C4-C16] disulfide pattern based on homology with closely related mu-conotoxins. The two major isomers of synthetic mu-KIIIA formed during oxidative folding were purified and their disulfide connectivities mapped by direct mass spectrometric collision-induced dissociation fragmentation of the disulfide-bonded polypeptides. Our results show that the major oxidative folding product adopts a C1-C15,C2-C9,C4-C16] disulfide connectivity, while the minor product adopts a C1-C16,C2-C9,C4-C15] connectivity. Both of these peptides were potent blockers of Na(v)1.2 (K-d values of 5 and 230 nM, respectively). The solution structure for mu-KIIIA based on nuclear magnetic resonance data was recalculated with the C1-C15,C2-C9,C4-C16] disulfide pattern; its structure was very similar to the mu-KIIIA structure calculated with the incorrect C1-C9,C2-C15,C4-C16] disulfide pattern, with an alpha-helix spanning residues 7-12. In addition, the major folding isomers of mu-KIIIB, an N-terminally extended isoform of mu-KIIIA, identified from its cDNA sequence, were isolated. These folding products had the same disulfide connectivities as mu-KIIIA, and both blocked Na(v)1.2 (K-d values of 470 and 26 nM, respectively). Our results establish that the preferred disulfide pattern of synthetic mu-KIIIA and mu-KIIIB folded in vitro is 1-5/2-4/3-6 but that other disulfide isomers are also potent sodium channel blockers. These findings raise questions about the disulfide pattern(s) of mu-KIIIA in the venom of Conus kinoshitai; indeed, the presence of multiple disulfide isomers in the venom could provide a means of further expanding the snail's repertoire of active peptides.

A Hybrid Five-Level Inverter With Common-Mode Voltage Elimination Having Single Voltage Source for IM Drive Applications

A new hybrid five-level inverter topology with common-mode voltage (CMV) elimination for induction motor drive is proposed in this paper. This topology has only one dc source, and different voltage levels are generated by using this voltage source along with floating capacitors charged to asymmetrical voltage levels. The pulsewidth modulation (PWM) scheme employed in this topology balances the capacitor voltages at the required levels at any power factor and modulation index while eliminating the CMV. This inverter has good fault-tolerant capability as it can be operated in three-or two-level mode with CMV elimination, in case of any failure in the H-bridges. More voltage levels with CMV elimination can be realized from this topology but only in a limited range of modulation index and power factor. Extensive simulation is done to validate the PWM technique for CMV elimination and balancing of the capacitor voltages. The experimental verification of the proposed inverter-fed induction motor is carried out in the linear modulation and overmodulation regions. The steady-state and transient operations of the drive are verified. The dynamics of the capacitor voltage balancing is also tested. The experimental results demonstrate that the proposed topology can be considered for industrial drive applications.

Multilevel Dodecagonal Voltage Space Vector Generation using Flying Capacitor topology for Induction motor drives

In this paper, a multilevel flying capacitor inverter topology suitable for generating multilevel dodecagonal space vectors for an induction motor drive, is proposed. Because of the dodecagonal space vectors, it has increased modulation range with the absence of all 6n +/- 1, (n=odd) harmonics in the phase voltage and currents. The topology, realized by flying capacitor three level inverters feeding an open-end winding induction motor, does not suffer the neutral point voltage imbalance issues seen in NPC inverters and the capacitors have inherent charge-balancing capability with PWM control using switching state redundancies. Furthermore, the proposed technique uses lesser number of power supplies compared to cascaded H-bridge or NPC based dodecagonal schemes and has better ride-through capability. Finally, the voltage control is obtained through a simple carrier-based space vector PWM scheme implemented on a DSP.

Evaluation of dynamic voltage and frequency scaling for stream programs

Dynamic Voltage and Frequency Scaling (DVFS) offers a huge potential for designing trade-offs involving energy, power, temperature and performance of computing systems. In this paper, we evaluate three different DVFS schemes - our enhancement of a Petri net performance model based DVFS method for sequential programs to stream programs, a simple profile based Linear Scaling method, and an existing hardware based DVFS method for multithreaded applications - using multithreaded stream applications, in a full system Chip Multiprocessor (CMP) simulator. From our evaluation, we find that the software based methods achieve significant Energy/Throughput2(ET−2) improvements. The hardware based scheme degrades performance heavily and suffers ET−2 loss. Our results indicate that the simple profile based scheme achieves the benefits of the complex Petri net based scheme for stream programs, and present a strong case for the need for independent voltage/frequency control for different cores of CMPs, which is lacking in most of the state-of-the-art CMPs. This is in contrast to the conclusions of a recent evaluation of per-core DVFS schemes for multithreaded applications for CMPs.

A Hybrid Multilevel Inverter System Based on Dodecagonal Space Vectors for Medium Voltage IM Drives

Dodecagonal (12-sided) space vector pulsewidth modulation (PWM) schemes are characterized by the complete absence of (6n +/- 1)th-order harmonics (for odd n) in the phase voltages, within the linear modulation range and beyond, including over-modulation. This paper presents a new topology suitable for the realization of such multilevel inverter schemes for induction motor (IM) drives, by cascading two-level inverters with flying-capacitor-inverter fed floating H-bridge cells. Now, any standard IM may be used to get the dodecagonal operation which hitherto was possible only with open-end winding IM. To minimize the current total harmonic distortion (THD), a strategy for synchronous PWM is also proposed. It is shown that the proposed method is capable of obtaining better THD figures, compared to conventional dodecagonal schemes. The topology and the PWM strategy are validated through analysis and subsequently verified experimentally.

Medium Voltage Drive for Induction Motors Using Multilevel Octadecagonal Voltage Space Vectors

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two-level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18-sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three-level inverters. By the proper selection of dc-link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector-based pulsewidth modulation (PWM) techniques are the complete elimination of fifth, seventh, eleventh, and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Experimental results have been presented in this paper to validate the proposed concept.

Threshold voltage model for accumulation mode polycrystalline SOI MOSFETs and comparisons with experimental results

In this paper, a simple but accurate semi analytical charge sheet model is presented for threshold voltage of accumulation mode polycrystalline silicon on insulator (PSOI) MOSFETs. In this model, we define the threshold voltage (V-T) of the polysilicon accumulation mode MOSFET as the gate voltage required to raise the surface potential (phi(s)) to a value phi(sT) necessary to overcome the charge trapping in the grain boundary and to create channel accumulation charge that is equal to the channel accumulation charge available in the case of single crystal silicon accumulation mode MOSFET at that phi(sT). The correctness of the model is demonstrated by comparing the theoretically estimated values of threshold voltage with the experimentally measured threshold voltages on the accumulation mode PSOI MOSFETs fabricated in the laboratory using LPCVD polysilicon layers doped with boron to achieve dopant densities in the range 3.3 x 10(-15)-5 x 10(17)/cm(3). Further, it is shown that the threshold voltage values of accumulation mode PSOI MOSFETs predicted by the present model match very closely with the experimental results, better than those obtained with the models previously reported in the literature. (C) 2012 Elsevier B.V. All rights reserved.

A Multilevel Inverter Scheme With Dodecagonal Voltage Space Vectors Based on Flying Capacitor Topology for Induction Motor Drives

This paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n +/- 1 (n = odd) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by flying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The flying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation.