Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys

It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features interconnection, operating frequency, the area on chip, power dissipation, performance and programmability. The mechanism of interconnection and communication it was considered ideal for this type of architecture are the networks-on-chip, due its scalability, reusability and intrinsic parallelism. The networks-on-chip communication is accomplished by transmitting packets that carry data and instructions that represent requests and responses between the processing elements interconnected by the network. The transmission of packets is accomplished as in a pipeline between the routers in the network, from source to destination of the communication, even allowing simultaneous communications between pairs of different sources and destinations. From this fact, it is proposed to transform the entire infrastructure communication of network-on-chip, using the routing mechanisms, arbitration and storage, in a parallel processing system for high performance. In this proposal, the packages are formed by instructions and data that represent the applications, which are executed on routers as well as they are transmitted, using the pipeline and parallel communication transmissions. In contrast, traditional processors are not used, but only single cores that control the access to memory. An implementation of this idea is called IPNoSys (Integrated Processing NoC System), which has an own programming model and a routing algorithm that guarantees the execution of all instructions in the packets, preventing situations of deadlock, livelock and starvation. This architecture provides mechanisms for input and output, interruption and operating system support. As proof of concept was developed a programming environment and a simulator for this architecture in SystemC, which allows configuration of various parameters and to obtain several results to evaluate it

Estudo da viabilidade do desenvolvimento de sistemas integrados baseados em redes em chip sem processadores: sistema IPNoSys

The increase of capacity to integrate transistors permitted to develop completed systems, with several components, in single chip, they are called SoC (System-on-Chip). However, the interconnection subsystem cans influence the scalability of SoCs, like buses, or can be an ad hoc solution, like bus hierarchy. Thus, the ideal interconnection subsystem to SoCs is the Network-on-Chip (NoC). The NoCs permit to use simultaneous point-to-point channels between components and they can be reused in other projects. However, the NoCs can raise the complexity of project, the area in chip and the dissipated power. Thus, it is necessary or to modify the way how to use them or to change the development paradigm. Thus, a system based on NoC is proposed, where the applications are described through packages and performed in each router between source and destination, without traditional processors. To perform applications, independent of number of instructions and of the NoC dimensions, it was developed the spiral complement algorithm, which finds other destination until all instructions has been performed. Therefore, the objective is to study the viability of development that system, denominated IPNoSys system. In this study, it was developed a tool in SystemC, using accurate cycle, to simulate the system that performs applications, which was implemented in a package description language, also developed to this study. Through the simulation tool, several result were obtained that could be used to evaluate the system performance. The methodology used to describe the application corresponds to transform the high level application in data-flow graph that become one or more packages. This methodology was used in three applications: a counter, DCT-2D and float add. The counter was used to evaluate a deadlock solution and to perform parallel application. The DCT was used to compare to STORM platform. Finally, the float add aimed to evaluate the efficiency of the software routine to perform a unimplemented hardware instruction. The results from simulation confirm the viability of development of IPNoSys system. They showed that is possible to perform application described in packages, sequentially or parallelly, without interruptions caused by deadlock, and also showed that the execution time of IPNoSys is more efficient than the STORM platform

Avaliação da execução de aplicações orientadas à dados na arquitetura de redes em chip IPNoSys

The increasing complexity of integrated circuits has boosted the development of communications architectures like Networks-on-Chip (NoCs), as an architecture; alternative for interconnection of Systems-on-Chip (SoC). Networks-on-Chip complain for component reuse, parallelism and scalability, enhancing reusability in projects of dedicated applications. In the literature, lots of proposals have been made, suggesting different configurations for networks-on-chip architectures. Among all networks-on-chip considered, the architecture of IPNoSys is a non conventional one, since it allows the execution of operations, while the communication process is performed. This study aims to evaluate the execution of data-flow based applications on IPNoSys, focusing on their adaptation against the design constraints. Data-flow based applications are characterized by the flowing of continuous stream of data, on which operations are executed. We expect that these type of applications can be improved when running on IPNoSys, because they have a programming model similar to the execution model of this network. By observing the behavior of these applications when running on IPNoSys, were performed changes in the execution model of the network IPNoSys, allowing the implementation of an instruction level parallelism. For these purposes, analysis of the implementations of dataflow applications were performed and compared

Implementação da técnica de software pipelining na rede em chip IPNoSyS

Alongside the advances of technologies, embedded systems are increasingly present in our everyday. Due to increasing demand for functionalities, many tasks are split among processors, requiring more efficient communication architectures, such as networks on chip (NoC). The NoCs are structures that have routers with channel point-to-point interconnect the cores of system on chip (SoC), providing communication. There are several networks on chip in the literature, each with its specific characteristics. Among these, for this work was chosen the Integrated Processing System NoC (IPNoSyS) as a network on chip with different characteristics compared to general NoCs, because their routing components also accumulate processing function, ie, units have functional able to execute instructions. With this new model, packets are processed and routed by the router architecture. This work aims at improving the performance of applications that have repetition, since these applications spend more time in their execution, which occurs through repeated execution of his instructions. Thus, this work proposes to optimize the runtime of these structures by employing a technique of instruction-level parallelism, in order to optimize the resources offered by the architecture. The applications are tested on a dedicated simulator and the results compared with the original version of the architecture, which in turn, implements only packet level parallelism

A label-free immunosensor based on recordable compact disk chip for early diagnostic of the dengue virus infection

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Fabricação de microcanais para integração de uma língua eletrônica em um sistema lab-on-a-chip

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Fatores de transcrição reguladores do metabolismo do glicogênio em Neurospora crassa: caracterização parcial e identificação de alvos de ligação por ChIP-Seq

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Método de inversão matricial rápido GSGR para vectoring em sistemas xDSL, com implementação em chip DSP

Este trabalho apresenta um método rápido de inversão de matrizes densas, e uma possível aplicação com métodos de Vectoring, em pré-codificação e cancelamento de crosstalk de sistemas xDSL. A família de tecnologias xDSL utiliza os pares trançados de fios de cobre telefônicos como meio físico para transmitir dados digitais. O crosstalk é a principal causa de degradação de sinais na mais nova geração de sistemas xDSL, o G.fast, e para combatê-lo são utilizadas técnicas de pré-codificação e cancelamento, chamadas de Vectoring. O método proposto, chamado de GSGR, consiste em uma abordagem diferente para o método clássico de Squared Givens Rotations (SGR), adequado a implementações em plataformas embarcadas de processamento digital de sinais. Foram realizados testes comparativos do método GSGR com métodos diretos clássicos de inversão, utilizando uma plataforma digital multicore baseada no chip TI DSP TMS320C6670 e a plataforma de software Matlab. Os resultados dos testes de inversão de matrizes usando dados reais e dados simulados mostraram que o GSGR foi superior em velocidade de execução sem apresentar perdas significativas de acurácia para a aplicação em sistemas xDSL.

Linkage disequilibrium levels in Bos indicus and Bos taurus cattle using medium and high density SNP chip data and different minor allele frequency distributions

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

ChIP-seq reveals a role for CrzA in the Aspergillus fumigatus high-osmolarity glycerol response (HOG) signalling pathway

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Padronização das atividades de manutenção para implementação de um projeto de TPM

La mission de ce rapport se trouvée dans un projet major de mise en place de la TPM dans l’usine de Biotechnologie à Huningue. Le même sera utilisé comme pilote pour les autres sites de l’entreprise. Le but spécifique de ma mission au sein de Novartis, était d’identifier les activités principales des équipes de maintenance, étudier la façon de travailler et la manière comment ils étaient renseignées dans leurs Ordres de Travail (OT). Ensuite, proposer un standard de flux de travail et façon de renseigner les OT et ainsi organiser la façon de travailler et pouvoir planifier les activités de maintenance, ayant une bonne base de données pour faire les indicateurs

Implementação da metodologia TPM em uma indústria do setor de higiene pessoal, saúde e beleza

This work presents a project of Action Search in a consumption industry of the sector of personal care, health and beauty. Following the implementation steps of Autonomous Maintenance Pillar of TPM methodology, stands for Total Productive Maintenance, this work aims to ensure the advancement of some machines in a production line of the company to the next steps of the methodology implementation, demonstrating the results achieved by the TPM. In the company in question, the TPM has been implemented in the past but lost strength over the years and some of its concepts were abandoned, producing then a drop in the equipments efficiency, increased wastes and breaks in the processes, as well as loss in product quality. Then, the need arose to restart the implementation process from the beginning, to strictly follow all the steps of the methodology, ensuring increased efficiency of equipment and processes. Through training and a changing in the company culture, it was possible a joint effort between Operation and Maintenance in order to enhance the knowledge of the operators on their machines. Initially, it was developed a general cleanliness program of equipments so that it could be possible to find the anomalies in the process. Subsequently, operators and maintainers were trained to detect anomalies, enabling equipments to work under their basic conditions of operation and subsequently building provisional standards of equipment cleaning, lubrication and inspection. Through the improvement presented by some indicators such as OEE, wastes, bankruptcies and unavailability, it was proved the importance and the positive effects of TPM implementation in manufacturing

Análise da implantação do TPM em uma empresa do ramo farmacêutico

Through observation of the production process industries today, one can encounter the needs of the large uncertainties related improvements and changes in the production environment, a fact that inspired the search for solutions that can respond quickly to these changes. Thus, this paper describes the review of implementation of TPM (total productivity management), which aims to optimize two distinct processes in the Vale do Paraíba´s pharmaceutical industry one of through the pillar of specific improvement. The main objective is to propose an efficient alternative to proposing loss management processes by identifying and eliminating the same in a systematic process. To develop this analysis was necessary to explore concepts of TPM and tools that help in taking data, identification and clarification of the phenomena that cause failures in the process, which were essential to ensure the development of the analysis. The concepts covered are usually presented during an undergraduate degree in Engineering. Data compiled by the analysis are able to serve as a strategic benchmark for decision making by managers, providing alternative response variables and uncertainty of the organizational environment, a fact that facilitates the management of human resources and productive

Dispositivo microfluídico de borracha natural (LAB-ON-A-CHIP)

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

A flexible lab-on-a-chip for the synthesis and magnetic separation of magnetite decorated with gold nanoparticles

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)