Optimization and finite element analysis for reliable electronic packaging

This paper demonstrates a modeling and design approach that couples computational mechanics techniques with numerical optimisation and statistical models for virtual prototyping and testing in different application areas concerning reliability of eletronic packages. The integrated software modules provide a design engineer in the electronic manufacturing sector with fast design and process solutions by optimizing key parameters and taking into account complexity of certain operational conditions. The integrated modeling framework is obtained by coupling the multi-phsyics finite element framework - PHYSICA - with the numerical optimisation tool - VisualDOC into a fully automated design tool for solutions of electronic packaging problems. Response Surface Modeling Methodolgy and Design of Experiments statistical tools plus numerical optimisaiton techniques are demonstrated as a part of the modeling framework. Two different problems are discussed and solved using the integrated numerical FEM-Optimisation tool. First, an example of thermal management of an electronic package on a board is illustrated. Location of the device is optimized to ensure reduced junction temperature and stress in the die subject to certain cooling air profile and other heat dissipating active components. In the second example thermo-mechanical simulations of solder creep deformations are presented to predict flip-chip reliability and subsequently used to optimise the life-time of solder interconnects under thermal cycling.

No-flow underfill flip chip assembly–an experimental and modeling analysis

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal–mechanical fatigue life of flip chips with no-flow underfill.

Reliability predictions for high density packaging

Predicting the reliability of newly designed products, before manufacture, is obviously highly desirable for many organisations. Understanding the impact of various design variables on reliability allows companies to optimise expenditure and release a package in minimum time. Reliability predictions originated in the early years of the electronics industry. These predictions were based on historical field data which has evolved into industrial databases and specifications such as the famous MIL-HDBK-217 standard, plus numerous others. Unfortunately the accuracy of such techniques is highly questionable especially for newly designed packages. This paper discusses the use of modelling to predict the reliability of high density flip-chip and BGA components. A number of design parameters are investigated at the assembly stage, during testing, and in-service.

Effects of reflow process on the reliability of flip chip on flex interconnections using anisotropic conductive adhesives

In this paper, the effects of the solder reflow process on the reliability of anisotropic conductive film (ACF) interconnections for flip chip on flex (FCOF) applications are investigated. Experiments as well as computer modeling methods have been used. In the experiments, it was found that the contact resistance of ACF joints increased after the subsequent reflow process, and the magnitude of this increase was strongly correlated to the peak temperature of the reflow profile. Nearly 40% of the joints were opened (i.e. lifted away from the pad) after the reflow process with 260 °C peak temperature while no opening was observed when the peak temperature was 210 °C. It is believed that the CTE mismatch between the polymer particle and the adhesive matrix is the main cause of this contact degradation. It was also found that the ACF joints after the reflow process with 210 °C peak temperature showed a high ability to resist water absorption under steady state 85 °C/85%RH conditions, probably because the curing degree of the ACF was improved during the reflow process. To give a good understanding, a 3D model of an ACF joint structure was built and finite element analysis was used to predict the stress distribution in the conductive particles, adhesive matrix and metal pads during the reflow process.

Predicting the relationship between reliability and geometric parameters of cu column bumped flip-chips

Cu column bumping is a novel flip chip packaging technique that allows Cu columns to be bonded directly with the dies. It has eliminated the under-bump-metallurgy (UBM) fonnation step of the traditional flip chip manufacturing process. This bumping technique has the potential benefits of simplifying the flip chip manufacturing process, increasing productivity and the UO counts. In this paper, a study of reliability of Cu column bumped flip chips will be presented. Computer modelling methods have been used to predict the shape of solder joints and the response of flip chips to cyclic thermal-mechanical loading. The accumulated plastic strain energy at the corner solder joints has been used as an indicator of the solder joint reliability. Models with a wide range of design parameters have been compared for their reliability. The design parameters that have been investigated are the copper column height and radius, PCB pad radius, solder volume and Cu column wetting height. The relative importance ranking of these parameters has been obtained. The Lead-free solder material 96.5Sn3.5Ag has been used in this modelling work.

A modelling and experimental analysis of the no-flow underfill process for flip-chip assembly

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfills as the application and curing of this type of underfill can be undertaken before and during the reflow process - adding high volume throughput. Adopting a no-flow underfill process may result in underfill entrapment between solder and fluid, voiding in the underfill, a possible delamination between underfill and surrounding surfaces. The magnitude of these phenomena may adversely affect the reliability of the assembly in terms of solder joint thermal fatigue. This paper presents both an experimental and mdeling analysis investigating the reliabity of a flip-chip component and how the magnitude of underfill entrapment may affect thermal-mechanical fatigue life.

Macro-Micro Modelling Analysis for High Density Packaged Flip Chips

A wide range of flip chip technologies with solder or adhesives have become dominant solutions for high density packaging applications due to the excellent electrical performance, high I/O density and good thermal performance. This paper discusses the use of modeling technique to predict the reliability of high density packaged flip chips in the humid environment. Reliability assessment is discussed for flip chip package at ultra-fine pitch with anisotropic conductive film (ACF). The purpose of this modeling work is to understand the role that moisture plays in the failure of ACF flip chips. A macro-micro 3D finite element modeling technique was used in order to make the multi-length-scale modeling of the ACF flip chip possible. Modeling results are consistent with the findings in the experimental work

Experimental and Modelling Analysis on the Moisture Induced Failures in Flip Chip on Flex Interconnections with Anisotropic Conductive Film

This paper reports the investigations into the moisture induced failures in flip-chip-on-flex interconnections with anisotropic conductive films (ACF). Both experimental and modeling methods were applied. In the experiments, the contact resistance was used as a quality indicator and was measured continuously during the accelerated tests (autoclave tests). The temperature, relative humidity and the pressure were set at 121°C, 100%RH, 1atm respectively. The contact resistance of the ACF joints increased during the tests and nearly 25% of the joints were found to be open after 168 hours' testing time. Visible conduction gaps between the adhesive and substrate pads were observed. Cracks at the adhesive/flex interface were also found. It is believed that the swelling effect of the adhesive and the water penetration along the adhesive/flex interface are the main causes of this contact degradation. Another finding from the experimental work was that the ACF interconnections that had undergone the reflow treatment were more sensitive to the moisture and showed worse reliability during the tests. For a better understanding of the experimental results, 3D finite element (FE) models were built and a macro-micro modeling method was used to determine the moisture diffusion and moisture-induced stresses inside the ACF joints. Modeling results are consistent with the findings in the experimental work.

Wire bond reliability for power electronic modules - effect of bonding temperature

In this paper, thermal cycling reliability along with ANSYS analysis of the residual stress generated in heavy-gauge Al bond wires at different bonding temperatures is reported. 99.999% pure Al wires of 375 mum in diameter, were ultrasonically bonded to silicon dies coated with a 5mum thick Al metallisation at 25degC (room temperature), 100degC and 200degC, respectively (with the same bonding parameters). The wire bonded samples were then subjected to thermal cycling in air from -60degC to +150degC. The degradation rate of the wire bonds was assessed by means of bond shear test and via microstructural characterisation. Prior to thermal cycling, the shear strength of all of the wire bonds was approximately equal to the shear strength of pure aluminum and independent of bonding temperature. During thermal cycling, however, the shear strength of room temperature bonded samples was observed to decrease more rapidly (as compared to bonds formed at 100degC and 200degC) as a result of a high crack propagation rate across the bonding area. In addition, modification of the grain structure at the bonding interface was also observed with bonding temperature, leading to changes in the mechanical properties of the wire. The heat and pressure induced by the high temperature bonding is believed to promote grain recovery and recrystallisation, softening the wires through removal of the dislocations and plastic strain energy. Coarse grains formed at the bonding interface after bonding at elevated temperatures may also contribute to greater resistance for crack propagation, thus lowering the wire bond degradation rate

Reliability based design optimisation for system-in-package

This paper discusses a reliability based optimisation modelling approach demonstrated for the design of a SiP structure integrated by stacking dies one upon the other. In this investigation the focus is on the strategy for handling the uncertainties in the package design inputs and their implementation into the design optimisation modelling framework. The analysis of fhermo-mechanical behaviour of the package is utilised to predict the fatigue life-time of the lead-free board level solder interconnects and warpage of the package under thermal cycling. The SiP characterisation is obtained through the exploitation of Reduced Order Models (ROM) constructed using high fidelity analysis and Design of Experiments (DoE) methods. The design task is to identify the optimal SiP design specification by varying several package input parameters so that a specified target reliability of the solder joints is achieved and in the same time design requirements and package performance criteria are met

Shear strength analysis of ball grid array (BGA) solder interfaces

Ball shear test is the most common test method used to assess the reliability of bond strength for ball grid array (BGA) packages. In this work, a combined experimental and numerical study was carried out to realize of BGA solder interface strength. Solder mask defined bond pads on the BGA substrate were used for BGA ball bonding. Different bond pad metallizations and solder alloys were used. Solid state aging at 150degC up to 1000 h has been carried out to change the interfacial microstructure. Cross-sectional studies of the solder-to-bond pad interfaces was conducted by scanning electron microscopy (SEM) equipped with an energy dispersive X-ray (EDX) analyzer to investigate the interfacial reaction phenomena. Ball shear tests have been carried out to obtain the mechanical strength of the solder joints and to correlate shear behaviour with the interfacial reaction products. An attempt has been taken to realize experimental findings by Finite Element Analysis (FEA). It was found that intermetallic compound (IMC) formation at the solder interface plays an important role in the BGA solder bond strength. By changing the morphology and the microchemistry of IMCs, the fracture propagation path could be changed and hence, reliability could be improved

Optimizing the reliability of power electronics module isolation substrates

Optimal design of a power electronics module isolation substrate is assessed using a combination of finite element structural mechanics analysis and response surface optimisation technique. Primary failure modes in power electronics modules include the loss of structural integrity in the ceramic substrate materials due to stresses induced through thermal cycling. Analysis of the influence of ceramic substrate design parameters is undertaken using a design of experiments approach. Finite element analysis is used to determine the stress distribution for each design, and the results are used to construct a quadratic response surface function. A particle swarm optimisation algorithm is then used to determine the optimal substrate design. Analysis of response surface function gradients is used to perform sensitivity analysis and develop isolation substrate design rules. The influence of design uncertainties introduced through manufacturing tolerances is assessed using a Monte-Carlo algorithm, resulting in a stress distribution histogram. The probability of failure caused by the violation of design constraints has been analyzed. Six geometric design parameters are considered in this work and the most important design parameters have been identified. Overall analysis results can be used to enhance the design and reliability of the component.

Numerical analysis of thermal stresses induced during VFM encapsulant curing

Encapsulant curing using a Variable Frequency Microwave (VFM) system is analysed numerically. Thermosetting polymer encapsulant materials require an input of heat energy to initiate the cure process. In this article, the heating is considered to be performed by a novel microwave system, able to perform the curing process more rapidly than conventional techniques. Thermal stresses are induced when packages containing materials with differing coefficients of thermal expansion are heated, and cure stresses are induced as thermosetting polymer materials shrink during the cure process. These stresses are developed during processing and remain as residual stresses within the component after the manufacturing process is complete. As residual stresses will directly affect the reliability of the device, it is necessary to assess their magnitude and the effect on package reliability. A coupled multiphysics model has been developed to numercially analyse the microwave curing process. In order to obtain a usefully accurate model of this process, a holistic approach has been taken, in which the process is not considered to be a sequence of discrete steps, but as a complex coupled system. An overview of the implemented numerical model is presented, with particular focus paid to analysis of induced thermal stresses. Results showing distribution of stresses within an idealised microelectronics package are presented and discussed.

Fracture mechanics analysis of cracks in solder joint intermetallic compounds

The trend towards miniaturization of electronic products leads to the need for very small sized solder joints. Therefore, there is a higher reliability risk that too large a fraction of solder joints will transform into Intermetallic Compounds (IMCs) at the solder interface. In this paper, fracture mechanics study of the IMC layer for SnPb and Pb-free solder joints was carried out using finite element numerical computer modelling method. It is assumed that only one crack is present in the IMC layer. Linear Elastic Fracture Mechanics (LEFM) approach is used for parametric study of the Stress Intensity Factors (SIF, KI and KII), at the predefined crack in the IMC layer of solder butt joint tensile sample. Contrary to intuition, it is revealed that a thicker IMC layer in fact increases the reliability of solder joint for a cracked IMC. Value of KI and KII are found to decrease with the location of the crack further away from the solder interfaces while other parameters are constant. Solder thickness and strain rate were also found to have a significant influence on the SIF values. It has been found that soft solder matrix generates non-uniform plastic deformation across the solder-IMC interface near the crack tip that is responsible to obtain higher KI and KII.

Design for reliability for wafer level system in package

This paper discusses the Design for Reliability modelling of several System-in-Package (SiP) structures developed by NXP and advanced on the basis of Wafer Level Packaging (WLP). Two different types of Wafer Level SiP (WLSiP) are presented and discussed. The main focus is on the modelling approach that has been adopted to investigate and analyse the board level reliability of the presented SiP configurations. Thermo-mechanical non-linear Finite Element Analysis (FEA) is used to analyse the effect of various package design parameters on the reliability of the structures and to identify design trends towards package optimisation. FEA is used also to gain knowledge on moulded wafer shrinkage and related issues during the wafer level fabrication. The paper provides a brief outline and demonstration of a design methodology for reliability driven design optimisation of SiP. The study emphasises the advantages of applying the methodology to address complex design problems where several requirements may exist and uncertainties and interactions between parameters in the design are common.