930 resultados para Multilayer
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Primarily targeted toward the network or MIS manager who wants to stay abreast of the latest networking technology, Enterprise Networking: Multilayer Switching and Applications offers up to date information relevant for the design of modern corporate networks and for the evaluation of new networking equipment. The book describes the architectures and standards of switching across the various protocol layers and will also address issues such as multicast quality of service, high-availability and network policies that are requirements of modern switched networks.
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We demonstrate surface plasmon resonance (SPR) fiber devices based upon ultraviolet inscription of a grating-type structure into both single-layered and multilayered thin films deposited on the flat side of a lapped D-shaped fiber. The single-layered devices were fabricated from germanium, while the multilayered ones comprised layers of germanium, silica, and silver. Some of the devices operated in air with high coupling efficiency in excess of 40 dB and an estimated index sensitivity of Delta lambda/Delta n = 90 mn from 1 to 1.15 index range, while others provided an index sensitivity of Delta lambda/Delta n = 6790 mn for refractive indices from 1.33 to 1.37. (C) 2009 Optical Society of America
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We obtained an analytical expression for the computational complexity of many layered committee machines with a finite number of hidden layers (L < 8) using the generalization complexity measure introduced by Franco et al (2006) IEEE Trans. Neural Netw. 17 578. Although our result is valid in the large-size limit and for an overlap synaptic matrix that is ultrametric, it provides a useful tool for inferring the appropriate architecture a network must have to reproduce an arbitrary realizable Boolean function.
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This Brief Report presents giant extraordinary Hall effect (EHE) in the Ru-mediated antiferromagnetically coupled [Pt/Co]5/Ru/[Co/Pt]5 multilayers (MLs) compared with those MLs without the Ru spacer. The enhancement of the EHE is attributed to the strong Ru/Co interface scattering. Through the variation in the Pt layer thickness and the temperature, we determine the relation between the Hall voltage and the longitudinal resistivity. It is found that the conventional scaling analysis has difficulties in consistently interpreting our data.
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This letter experimentally demonstrates a visible light communication system using a 350-kHz polymer lightemitting diode operating at a total bit rate of 19 Mb/s with a bit error rate (BER) of 10-6and 20 Mb/s at the forward error correction limit for the first time. This represents a remarkable net data rate gain of ~55 times. The modulation format adopted is ON-OFF keying in conjunction with an artificial neural network classifier implemented as an equalizer. The number of neurons used in the experiment is varied from the set N = {5, 10, 20, 30, 40} with 40 neurons offering the best performance at 19 Mb/s and the BER of 10-6.
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The Artificial Neural Networks (ANN), which is one of the branches of Artificial Intelligence (AI), are being employed as a solution to many complex problems existing in several areas. To solve these problems, it is essential that its implementation is done in hardware. Among the strategies to be adopted and met during the design phase and implementation of RNAs in hardware, connections between neurons are the ones that need more attention. Recently, are RNAs implemented both in application specific integrated circuits's (Application Specific Integrated Circuits - ASIC) and in integrated circuits configured by the user, like the Field Programmable Gate Array (FPGA), which have the ability to be partially rewritten, at runtime, forming thus a system Partially Reconfigurable (SPR), the use of which provides several advantages, such as flexibility in implementation and cost reduction. It has been noted a considerable increase in the use of FPGAs for implementing ANNs. Given the above, it is proposed to implement an array of reconfigurable neurons for topologies Description of artificial neural network multilayer perceptrons (MLPs) in FPGA, in order to encourage feedback and reuse of neural processors (perceptrons) used in the same area of the circuit. It is further proposed, a communication network capable of performing the reuse of artificial neurons. The architecture of the proposed system will configure various topologies MLPs networks through partial reconfiguration of the FPGA. To allow this flexibility RNAs settings, a set of digital components (datapath), and a controller were developed to execute instructions that define each topology for MLP neural network.
Resumo:
The Artificial Neural Networks (ANN), which is one of the branches of Artificial Intelligence (AI), are being employed as a solution to many complex problems existing in several areas. To solve these problems, it is essential that its implementation is done in hardware. Among the strategies to be adopted and met during the design phase and implementation of RNAs in hardware, connections between neurons are the ones that need more attention. Recently, are RNAs implemented both in application specific integrated circuits's (Application Specific Integrated Circuits - ASIC) and in integrated circuits configured by the user, like the Field Programmable Gate Array (FPGA), which have the ability to be partially rewritten, at runtime, forming thus a system Partially Reconfigurable (SPR), the use of which provides several advantages, such as flexibility in implementation and cost reduction. It has been noted a considerable increase in the use of FPGAs for implementing ANNs. Given the above, it is proposed to implement an array of reconfigurable neurons for topologies Description of artificial neural network multilayer perceptrons (MLPs) in FPGA, in order to encourage feedback and reuse of neural processors (perceptrons) used in the same area of the circuit. It is further proposed, a communication network capable of performing the reuse of artificial neurons. The architecture of the proposed system will configure various topologies MLPs networks through partial reconfiguration of the FPGA. To allow this flexibility RNAs settings, a set of digital components (datapath), and a controller were developed to execute instructions that define each topology for MLP neural network.
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A facile spin cast route was developed to convert perpendicularly aligned nanorod assemblies of cadmium chalcogenides into their silver and copper analogues. The assemblies are rapidly cation exchanged without affecting either the individual rod dimensions or collective superlattice order extending over several multilayers.
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A binder-free cobalt phosphate hydrate (Co3(PO4)2·8H2O) multilayer nano/microflake structure is synthesized on nickel foam (NF) via a facile hydrothermal process. Four different concentrations (2.5, 5, 10, and 20 mM) of Co2+ and PO4–3 were used to obtain different mass loading of cobalt phosphate on the nickel foam. The Co3(PO4)2·8H2O modified NF electrode (2.5 mM) shows a maximum specific capacity of 868.3 C g–1 (capacitance of 1578.7 F g–1) at a current density of 5 mA cm–2 and remains as high as 566.3 C g–1 (1029.5 F g–1) at 50 mA cm–2 in 1 M NaOH. A supercapattery assembled using Co3(PO4)2·8H2O/NF as the positive electrode and activated carbon/NF as the negative electrode delivers a gravimetric capacitance of 111.2 F g–1 (volumetric capacitance of 4.44 F cm–3). Furthermore, the device offers a high specific energy of 29.29 Wh kg–1 (energy density of 1.17 mWh cm–3) and a specific power of 4687 W kg–1 (power density of 187.5 mW cm–3).
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In modern power electronics equipment, it is desirable to design a low profile, high power density, and fast dynamic response converter. Increases in switching frequency reduce the size of the passive components such as transformers, inductors, and capacitors which results in compact size and less requirement for the energy storage. In addition, the fast dynamic response can be achieved by operating at high frequency. However, achieving high frequency operation while keeping the efficiency high, requires new advanced devices, higher performance magnetic components, and new circuit topology. These are required to absorb and utilize the parasitic components and also to mitigate the frequency dependent losses including switching loss, gating loss, and magnetic loss. Required performance improvements can be achieved through the use of Radio Frequency (RF) design techniques. To reduce switching losses, resonant converter topologies like resonant RF amplifiers (inverters) combined with a rectifier are the effective solution to maintain high efficiency at high switching frequencies through using the techniques such as device parasitic absorption, Zero Voltage Switching (ZVS), Zero Current Switching (ZCS), and a resonant gating. Gallium Nitride (GaN) device technologies are being broadly used in RF amplifiers due to their lower on- resistance and device capacitances compared with silicon (Si) devices. Therefore, this kind of semiconductor is well suited for high frequency power converters. The major problems involved with high frequency magnetics are skin and proximity effects, increased core and copper losses, unbalanced magnetic flux distribution generating localized hot spots, and reduced coupling coefficient. In order to eliminate the magnetic core losses which play a crucial role at higher operating frequencies, a coreless PCB transformer can be used. Compared to the conventional wire-wound transformer, a planar PCB transformer in which the windings are laid on the Printed Board Circuit (PCB) has a low profile structure, excellent thermal characteristics, and ease of manufacturing. Therefore, the work in this thesis demonstrates the design and analysis of an isolated low profile class DE resonant converter operating at 10 MHz switching frequency with a nominal output of 150 W. The power stage consists of a class DE inverter using GaN devices along with a sinusoidal gate drive circuit on the primary side and a class DE rectifier on the secondary side. For obtaining the stringent height converter, isolation is provided by a 10-layered coreless PCB transformer of 1:20 turn’s ratio. It is designed and optimized using 3D Finite Element Method (FEM) tools and radio frequency (RF) circuit design software. Simulation and experimental results are presented for a 10-layered coreless PCB transformer operating in 10 MHz.
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Developing magnetic multilayers are essential for reducing the core eddy current losses in the integrated power magnetic components (inductors/transformers). PVD based processes are typically used to achieve the multilayers with thin dielectric spacers. However, those processes are costly, and can be difficult to integrate. It is evident that cost effective alternative is needed. In recent years, electrochemical processes have been investigated to address these issues. One such method would be to successive metallization of insulating photoresists acting as spacer layer (such as SU-8) with soft magnetic films (such as Ni-Fe-Co alloys). This paper describes an experimental procedure to fabricate magnetic multilayers with a thin variant of SU-8 2 (< 1.5 µm) as inter-layers for integrated micro-inductors/transformers for power conversion applications.
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The Node-based Local Mesh Generation (NLMG) algorithm, which is free of mesh inconsistency, is one of core algorithms in the Node-based Local Finite Element Method (NLFEM) to achieve the seamless link between mesh generation and stiffness matrix calculation, and the seamless link helps to improve the parallel efficiency of FEM. Furthermore, the key to ensure the efficiency and reliability of NLMG is to determine the candidate satellite-node set of a central node quickly and accurately. This paper develops a Fast Local Search Method based on Uniform Bucket (FLSMUB) and a Fast Local Search Method based on Multilayer Bucket (FLSMMB), and applies them successfully to the decisive problems, i.e. presenting the candidate satellite-node set of any central node in NLMG algorithm. Using FLSMUB or FLSMMB, the NLMG algorithm becomes a practical tool to reduce the parallel computation cost of FEM. Parallel numerical experiments validate that either FLSMUB or FLSMMB is fast, reliable and efficient for their suitable problems and that they are especially effective for computing the large-scale parallel problems.