The spatiotemporal dynamics of autobiographical memory: neural correlates of recall, emotional intensity, and reliving.

We sought to map the time course of autobiographical memory retrieval, including brain regions that mediate phenomenological experiences of reliving and emotional intensity. Participants recalled personal memories to auditory word cues during event-related functional magnetic resonance imaging (fMRI). Participants pressed a button when a memory was accessed, maintained and elaborated the memory, and then gave subjective ratings of emotion and reliving. A novel fMRI approach based on timing differences capitalized on the protracted reconstructive process of autobiographical memory to segregate brain areas contributing to initial access and later elaboration and maintenance of episodic memories. The initial period engaged hippocampal, retrosplenial, and medial and right prefrontal activity, whereas the later period recruited visual, precuneus, and left prefrontal activity. Emotional intensity ratings were correlated with activity in several regions, including the amygdala and the hippocampus during the initial period. Reliving ratings were correlated with activity in visual cortex and ventromedial and inferior prefrontal regions during the later period. Frontopolar cortex was the only brain region sensitive to emotional intensity across both periods. Results were confirmed by time-locked averages of the fMRI signal. The findings indicate dynamic recruitment of emotion-, memory-, and sensory-related brain regions during remembering and their dissociable contributions to phenomenological features of the memories.

Identification of pertussis-specific effector memory T cells in preschool children

Whooping cough remains a problem despite vaccination, and worldwide resurgence of pertussis is evident. Since cellular immunity plays a role in long-term protection against pertussis, we studied pertussis-specific T-cell responses. Around the time of the preschool acellular pertussis (aP) booster dose at 4 years of age, T-cell memory responses were compared in children who were primed during infancy with either a whole-cell pertussis (wP) or an aP vaccine. Peripheral blood mononuclear cells (PBMCs) were isolated and stimulated with pertussis vaccine antigens for 5 days. T cells were characterized by flow-based analysis of carboxyfluorescein succinimidyl ester (CFSE) dilution and CD4, CD3, CD45RA, CCR7, gamma interferon (IFN-γ), and tumor necrosis factor alpha (TNF-α) expression. Before the aP preschool booster vaccination, both the proliferated pertussis toxin (PT)-specific CD4⁺ and CD8⁺ T-cell fractions (CFSE^dim) were higher in aP-than in wP-primed children. Post-booster vaccination, more pertussis-specific CD4⁺ effector memory cells (CD45RA^- CCR7^-) were induced in aP-primed children than in those primed with wP. The booster vaccination did not appear to significantly affect the T-cell memory subsets and functionality in aP-primed or wP-primed children. Although the percentages of Th1 cytokine-producing cells were alike in aP- and wP-primed children pre-booster vaccination, aP-primed children produced more Th1 cytokines due to higher numbers of proliferated pertussis-specific effector memory cells. At present, infant vaccinations with four aP vaccines in the first year of life result in pertussis-specific CD4⁺ and CD8⁺ effector memory T-cell responses that persist in children until 4 years of age and are higher than those in wP-primed children. The booster at 4 years of age is therefore questionable; this may be postponed to 6 years of age.

Different T cell memory in preadolescents after whole-cell or acellular pertussis vaccination.

To better understand vaccine-induced protection and its potential failure in light of recent whooping cough resurgence, we evaluated quantity as well as quality of memory T cell responses in B. pertussis-vaccinated preadolescent children. Using a technique based on flow cytometry to detect proliferation, cytokine production and phenotype of antigen-specific cells, we evaluated residual T cell memory in a cohort of preadolescents who received a whole-cell pertussis (wP; n=11) or an acellular pertussis vaccine (aP; n=13) during infancy, and with a median of 4 years elapsed from the last pertussis booster vaccine, which was aP for all children. We demonstrated that B. pertussis-specific memory T cells are detectable in the majority of preadolescent children several years after vaccination. CD4(+) and CD8(+) T cell proliferation in response to pertussis toxin and/or filamentous hemagglutinin was detected in 79% and 60% of the children respectively, and interferon-γ or tumor necrosis factor-α producing CD4(+) T cells were detected in 65% and 53% of the children respectively. Phenotyping of the responding cells showed that the majority of antigen-specific cells, whether defined by proliferation or cytokine production, were CD45RA(-)CCR7(-) effector memory T cells. Although the time since the last booster vaccine was significantly longer for wP-compared to aP-vaccinated children, their proliferation capacity in response to antigenic stimulation was comparable, and more children had a detectable cytokine response after wP- compared to aP-vaccination. This study supports at the immunological level recent epidemiological studies indicating that infant vaccination with wP induces longer lasting immunity than vaccination with aP-vaccines.

Automatic parallel code generation for message passing on distributed memory systems

The availability of a very accurate dependence graph for a scalar code is the basis for the automatic generation of an efficient parallel implementation. The strategy for this task which is encapsulated in a comprehensive data partitioning code generation algorithm is described. This algorithm involves the data partition, calculation of assignment ranges for partitioned arrays, addition of a comprehensive set of execution control masks, altering loop limits, addition and optimisation of communications for all data. In this context, the development and implementation of strategies to merge communications wherever possible has proved an important feature in producing efficient parallel implementations for numerical mesh based codes. The code generation strategies described here are embedded within the Computer Aided Parallelisation tools (CAPTools) software as a key part of a toolkit for automating as much as possible of the parallelisation process for mesh based numerical codes. The algorithms used enables parallelisation of real computational mechanics codes with only minor user interaction and without any prior manual customisation of the serial code to suit the parallelisation tool.

A scalable strategy for the parallelization of multiphysics unstructured mesh-iterative codes on distributed-memory systems

Realizing scalable performance on high performance computing systems is not straightforward for single-phenomenon codes (such as computational fluid dynamics [CFD]). This task is magnified considerably when the target software involves the interactions of a range of phenomena that have distinctive solution procedures involving different discretization methods. The problems of addressing the key issues of retaining data integrity and the ordering of the calculation procedures are significant. A strategy for parallelizing this multiphysics family of codes is described for software exploiting finite-volume discretization methods on unstructured meshes using iterative solution procedures. A mesh partitioning-based SPMD approach is used. However, since different variables use distinct discretization schemes, this means that distinct partitions are required; techniques for addressing this issue are described using the mesh-partitioning tool, JOSTLE. In this contribution, the strategy is tested for a variety of test cases under a wide range of conditions (e.g., problem size, number of processors, asynchronous / synchronous communications, etc.) using a variety of strategies for mapping the mesh partition onto the processor topology.

Towards policy-based self-configuration of embedded systems

This paper describes work towards the deployment of flexible self-management into real-time embedded systems. A challenging project which focuses specifically on the development of a dynamic, adaptive automotive middleware is described, and the specific self-management requirements of this project are discussed. These requirements have been identified through the refinement of a wide-ranging set of use cases requiring context-sensitive behaviours. A sample of these use-cases is presented to illustrate the extent of the demands for self-management. The strategy that has been adopted to achieve self-management, based on the use of policies is presented. The embedded and real-time nature of the target system brings the constraints that dynamic adaptation capabilities must not require changes to the run-time code (except during hot update of complete binary modules), adaptation decisions must have low latency, and because the target platforms are resource-constrained the self-management mechanism have low resource requirements (especially in terms of processing and memory). Policy-based computing is thus and ideal candidate for achieving the self-management because the policy itself is loaded at run-time and can be replaced or changed in the future in the same way that a data file is loaded. Policies represent a relatively low complexity and low risk means of achieving self-management, with low run-time costs. Policies can be stored internally in ROM (such as default policies) as well as externally to the system. The architecture of a designed-for-purpose powerful yet lightweight policy library is described. A suitable evaluation platform, supporting the whole life-cycle of feasibility analysis, concept evaluation, development, rigorous testing and behavioural validation has been devised and is described.

Neural network based control for synchronous generators

In this paper, a Radial Basis Function neural network based AVR is proposed. A control strategy which generates local linear models from a global neural model on-line is used to derive controller feedback gains based on the Generalised Minimum Variance technique. Testing is carried out on a micromachine system which enables evaluation of practical implementation of the scheme. Constraints imposed by gathering training data, computational load, and memory requirements for the training algorithm are addressed.

How many processes underline category-based induction? Effect of conclusion specificity and cognitive ability

Two studies investigated participants' sensitivity to the amount and diversity of the evidence when reasoning inductively about categories. Both showed that participants are more sensitive to characteristics of the evidence for arguments with general rather than specific conclusions. Both showed an association between cognitive ability and sensitivity to these evidence characteristics, particularly when the conclusion category was general. These results suggest that a simple associative process may not be sufficient to capture some key phenomena of category-based induction. They also support the claim that the need to generate a superordinate category is a complicating factor in category-based reasoning and that adults' tendency to generate such categories while reasoning has been overestimated.

The soundscape as time capsule: A creative project based on the sounds of the first train station of Cuenca

This article reflects on the changing environment through the passage of time and how certain technologies for a creative proposal allow the preservation and transmission of a significant part of that ephemeral heritage for future generations. The general purpose of this particular project is aimed to achieve the sound synthesis of a specific and representative cityscape as the old train station in Cuenca –located in the heart of the city– that could be preserved and reproduced as an unique document of a present time, ascertainable in the future: a memory that interpret sound as a time capsule. This soundscape was made to mark the arrival of the high speed train in 2010 to a brand new station in the outskirts of the city. Therefore, the goal of this research was focused on achieving a synthetic document that provided a sound memory capable of reflecting the significant social, cultural and logistical features, of what was until then the only railway communication symbol in the city of Cuenca from 1883 to the first decade of the 21st century.

Digital Baseband Predistortion Based Linearized Broadband Inverse Class-E Power Amplifier

A newly introduced inverse class-E power amplifier (PA) was designed, simulated, fabricated, and characterized. The PA operated at 2.26 GHz and delivered 20.4-dBm output power with peak drain efficiency (DE) of 65% and power gain of 12 dB. Broadband performance was achieved across a 300-Mitz bandwidth with DE of better than 50% and 1-dB output-power flatness. The concept of enhanced injection predistortion with a capability to selectively suppress unwanted sub-frequency components and hence suitable for memory effects minimization is described coupled with a new technique that facilitates an accurate measurement of the phase of the third-order intermodulation (IM3) products. A robust iterative computational algorithm proposed in this paper dispenses with the need for manual tuning of amplitude and phase of the IM3 injected signals as commonly employed in the previous publications. The constructed inverse class-E PA was subjected to a nonconstant envelope 16 quadrature amplitude modulation signal and was linearized using combined lookup table (LUT) and enhanced injection technique from which superior properties from each technique can be simultaneously adopted. The proposed method resulted in 0.7% measured error vector magnitude (in rms) and 34-dB adjacent channel leakage power ratio improvement, which was 10 dB better than that achieved using the LUT predistortion alone.

SoC memory hierarchy derivation from dataflow graphs

Hardware synthesis from dataflow graphs of signal processing systems is a growing research area as focus shifts to high level design methodologies. For data intensive systems, dataflow based synthesis can lead to an inefficient usage of memory due to the restrictive nature of synchronous dataflow and its inability to easily model data reuse. This paper explores how dataflow graph changes can be used to drive both the on-chip and off-chip memory organisation and how these memory architectures can be mapped to a hardware implementation. By exploiting the data reuse inherent to many image processing algorithms and by creating memory hierarchies, off-chip memory bandwidth can be reduced by a factor of a thousand from the original dataflow graph level specification of a motion estimation algorithm, with a minimal increase in memory size. This analysis is verified using results gathered from implementation of the motion estimation algorithm on a Xilinx Virtex-4 FPGA, where the delay between the memories and processing elements drops from 14.2 ns down to 1.878 ns through the refinement of the memory architecture. Care must be taken when modeling these algorithms however, as inefficiencies in these models can be easily translated into overuse of hardware resources.

The Relevance Framework for Category-Based Induction: Evidence From Garden-Path Arguments

Relevance theory (Sperber & Wilson. 1995) suggests that people expend cognitive effort when processing information in proportion to the cognitive effects to be gained from doing so. This theory has been used to explain how people apply their knowledge appropriately when evaluating category-based inductive arguments (Medin, Coley, Storms, & Hayes, 2003). In such arguments, people are told that a property is true of premise categories and are asked to evaluate the likelihood that it is also true of conclusion categories. According to the relevance framework, reasoners generate hypotheses about the relevant relation between the categories in the argument. We reasoned that premises inconsistent with early hypotheses about the relevant relation would have greater effects than consistent premises. We designed three premise garden-path arguments where the same 3rd premise was either consistent or inconsistent with likely hypotheses about the relevant relation. In Experiments 1 and 2, we showed that effort expended processing consistent premises (measured via reading times) was significantly less than effort expended on inconsistent premises. In Experiment 2 and 3, we demonstrated a direct relation between cognitive effect and cognitive effort. For garden-path arguments, belief change given inconsistent 3rd premises was significantly correlated with Premise 3 (Experiment 3) and conclusion (Experiments 2 and 3) reading times. For consistent arguments, the correlation between belief change and reading times did not approach significance. These results support the relevance framework for induction but are difficult to accommodate under other approaches.

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.

XOR-based hash functions

Bank conflicts can severely reduce the bandwidth of an interleaved multibank memory and conflict misses increase the miss rate of a cache or a predictor. Both occurrences are manifestations of the same problem: Objects which should be mapped to different indices are accidentally mapped to the same index. Suitable chosen hash functions can avoid conflicts in each of these situations by mapping the most frequently occurring patterns conflict-free. A particularly interesting class of hash functions are the XOR-based hash functions, which compute each set index bit as the exclusive-or of a subset of the address bits. When implementing an XOR-based hash function, it is extremely important to understand what patterns are mapped conflict-free and how a hash function can be constructed to map the most frequently occurring patterns without conflicts. Hereto, this paper presents two ways to reason about hash functions: by their null space and by their column space. The null space helps to quickly determine whether a pattern is mapped conflict-free. The column space is more useful for other purposes, e. g., to reduce the fan-in of the XOR-gates without introducing conflicts or to evaluate interbank dispersion in skewed-associative caches. Examples illustrate how these ideas can be applied to construct conflict-free hash functions.

Predictive position and force control for shape memory alloy cylinders

In this paper, a linear lightweight electric cylinder constructed using shape memory alloy (SMA) is proposed. Spring SMA is used as the actuator to control the position and force of the cylinder rod. The model predictive control algorithm is investigated to compensate SMA hysteresis phenomenon and control the cylinder. In the predictive algorithm, the future output of the cylinder is computed based on the cylinder model, and the control signal is computed to minimize the error and power criterion. The cylinder model parameters are estimated by an online identification algorithm. Experimental results show that the SMA cylinder is able to precisely control position and force by using the predictive control strategy though the hysteresis effect existing in the actuator. The performance of the proposed controller is compared with that of a conventional PID controller