Simulation of a monolithically integrated CMOS bioamplifier for EEG recordings

A monolithically integrated CMOS bioamplifier is presented in this paper for EEG recording applications. The capacitive-coupled circuit input structure is utilized to eliminate the large and random DC offsets existing in the electrode-tissue interface. Diode-connected NMOS transistors with negative voltage between gate and source are candidates for large resistors necessary to the bioamplifier. A passive BEF (Band Eliminator Filter) can reduce 50 Hz noise disturbance strength by more than 60 dB. A novel analysis approach is given to help determine the noise power spectral density. Simulation results show that the two-stage CMOS bioamplifier in a closed-loop capacitive feedback configuration,provides an AC in-band gain of 39.6 dB, a DC gain of zero, and an input-referred noise of 87 nVrms integrated from 0.01 Hz to 100 Hz.

A CMOS front-end circuit for SONET OC-96 receiver

An optical receiver front-end for SONET OC-96 receivers was analyzed and designed in 0.18 mu m CMOS process. It consists of a transimpedance amplifier (TIA) and a limiting amplifier (LA). The TIA takes a fully differential configuration, and regulated cascode (RGC) input stage is implemented. The LA was realized by five cascaded identical gain stages with active inductor load. The TIA achieved 4.2GHz bandwidth for 0.5pF photodiode (PD) capacitance and 1.2k 0 transimpedance gain. The LA achieved 5.4GHz bandwidth and 29dB voltage gain. The optical sensitivity is -19dBm at 5-Gb/s for a bit-error rate of 10(-12), and it dissipates 45.5mW for I.8V supply.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Electroabsorption modulated semiconductor optical amplifier monolithically integrated with spot-size converters

We have demonstrated an electroabsorption modulator (EAM) and semiconductor optical amplifier (SOA) monolithically integrated with novel dual-waveguide spot-size converters (SSCs) at the input and output ports for low-loss coupling to planar light-guide circuit silica waveguide or cleaved single-mode optical fiber. The device is fabricated by means of selective-area MOVPE growth (SAG), quantum well intermixing (QWI) and asymmetric twin waveguide (ATG) technologies with only three steps low-pressure MOVPE growth. For the device structure, in SOA/EAM section, double ridge structure was employed to reduce the EAM capacitances and enable high bit-rate operation. In the SSC sections, buried ridge stripe (BRS) were incorporated. Such a combination of ridge, ATG and BRS structure is reported for the first time in which it can take advantage of both easy processing of ridge structure and the excellent mode characteristic of BRS. At the wavelength range of 1550-1600 nm, lossless operation with extinction ratios of 25 dB DC and more than 10 GHz 3-dB bandwidth is successfully achieved. The beam divergence angles of the input and output ports of the device are as small as 8.0 degrees x 12.6 degrees, resulting in 3.0 dB coupling loss with cleaved single-mode optical fiber. (c) 2005 Elsevier B.V. All rights reserved.

A simulation model of body contact structure in PD SOI analogue circuit

As a solution of accurate simulation of the body effect in PD SOI analogue circuit, a simulation model of distributed body contact resistance and parasitical capacitance is presented. Based on this model, we have designed and simulated a sense amplifier that applied to V a 0.8um PD SOI 64K SRAM.

Circuit design and simulation of a CMOS-based preamplifier for brain neural signals

A novel CMOS-based preamplifier for amplifying brain neural signal obtained by scalp electrodes in brain-computer interface (BCI) is presented in this paper. By means of constructing effective equivalent input circuit structure of the preamplifier, two capacitors of 5 pF are included to realize the DC suppression compared to conventional preamplifiers. Then this preamplifier is designed and simulated using the standard 0.6 mu m MOS process technology model parameters with a supply voltage of 5 volts. With differential input structures adopted, simulation results of the preamplifier show that the input impedance amounts to more than 2 Gohm with brain neural signal frequency of 0.5 Hz-100 Hz. The equivalent input noise voltage is 18 nV/Hz(1/2). The common mode rejection ratio (CMRR) of 112 dB and the open-loop differential gain of 90 dB are achieved.

Fabrication of a novel silica PLC hybrid integrated triplexer

A new-style silica planar lightwave circuit (PLC) hybrid integrated triplexer, which can demultiplex 1490-nm download data and 1550-nm download analog signals, as well as transmit 1310-nm upload data, is presented. It combines SiO2 arrayed waveguide gratings (AWGs) with integrated photodetectors (PDs) and a high performance laser diode (LD). The SiO2 AWGs realize the three-wavelength coarse wavelength-division multiplexing (CWDM). The crosstalk is less than 40 dB between the 1490- and 1550-nm channels, and less than 45 dB between 1310- and 1490- or 1550-nm channels. For the static performances of the integrated triplexer, its upload output power is 0.4 mW, and the download output photo-generated current is 76 A. In the small-signal measurement, the upstream 3-dB bandwidth of the triplexer is 4 GHz, while the downstream 3-dB bandwidths of both the analog and digital sections reach 1.9 GHz.

Simulation of a Monolithic Integrated CMOS Preamplifier for Neural Recordings

A monolithic integrated CMOS preamplifier is presented for neural recording applications. Two AC-coupied capacitors are used to eliminate the large and random DC offsets existing in the electrode-electrolyte interface. Diode-connected nMOS transistors with a negative voltage between the gate and source are candidates for the large resistors necessary for the preamplifier. A novel analysis is given to determine the noise power spectral density. Simulation results show that the two-stage CMOS preamplifier in a closed-loop capacitive feedback configuration provides an AC in-band gain of 38.8dB,a DC gain of 0,and an input-referred noise of 277nVmax, integrated from 0. 1Hz to 1kHz. The preamplifier can eliminate the DC offset voltage and has low input-referred noise by novel circuit configuration and theoretical analysis.

Co—Design of Monolithically Integrated Photo—Detectorand Optical—Receiver

A behavioral model of the photodiode is presented．The model describes the relationship between photocurrent and incident optical power，and it also illustrates the impact of the reverse bias to the variation of the junction capacitance．According to this model，the photodiode and a CMOS receiver circuit are simulated and designed simultaneously under a universal circuit simulation environment．

AN INTEGRATED CALCIUM-FLUORIDE CRYSTAL IR THIN-LAYER CELL AND ITS APPLICATION TO IDENTIFICATION OF ELECTROCHEMICAL REDUCTION PRODUCT OF BILIRUBIN

An integrated CaF2 crystal optically transparent infrared (ir) thin-layer cell was designed and constructed without using any soluble adhesive materials. It is suitable for both aqueous and nonaqueous systems, and can be used not only in ir but also in uv-vis studies. Excellent electrochemical and spectroelectrochemical responses were obtained in evaluating this cell by cyclic voltammetry and steady-state potential step measurements for both ir and uv-vis spectrolectrochemistry with ferri/ferrocyanide in aqueous solution, and with ferrocene/ferrocenium in organic solvent as the testing species, respectively. The newly designed ir cell was applied to investigate the electrochemical reduction process of bilirubin in situ, which provided direct information for identifying the structure of the reduction product and proposing the reaction mechanism.

An integrated air-POM syngas/dimethyl ether process from natural gas

A Cu-Zn-Al methanol catalyst combined with HZSM-5 was used for dimethyl ether (DME) synthesis from a syngas containing nitrogen, which was produced by air-partial oxidation of methane (air-POM). Air-POM occurred at 850 degreesC, 0.8 MPa, CH4/air/H2O/CO2 ratio of 1/2.4/0.8/0.4 over a Ni-based catalyst modified by magnesia and lanthanum oxide with 96% CH4 conversion and constantly gave syngas with a H-2/CO ratio of 2/1 during a period of 450 h. The obtained N-2-containing syngas was used directly for DME synthesis. About 90% CO per-pass conversion, 78% DME selectivity and 70% DME yield could be achieved during 450 h stability testing under the pressure of 5.0 MPa. the temperature of 240 degreesC and the space velocity of 1000 h(-1). (C) 2002 Elsevier Science B. V. All rights reserved.

An integrated firewall policy validation tool.

Security policies are increasingly being implemented by organisations. Policies are mapped to device configurations to enforce the policies. This is typically performed manually by network administrators. The development and management of these enforcement policies is a difficult and error prone task. This thesis describes the development and evaluation of an off-line firewall policy parser and validation tool. This provides the system administrator with a textual interface and the vendor specific low level languages they trust and are familiar with, but the support of an off-line compiler tool. The tool was created using the Microsoft C#.NET language, and the Microsoft Visual Studio Integrated Development Environment (IDE). This provided an object environment to create a flexible and extensible system, as well as simple Web and Windows prototyping facilities to create GUI front-end applications for testing and evaluation. A CLI was provided with the tool, for more experienced users, but it was also designed to be easily integrated into GUI based applications for non-expert users. The evaluation of the system was performed from a custom built GUI application, which can create test firewall rule sets containing synthetic rules, to supply a variety of experimental conditions, as well as record various performance metrics. The validation tool was created, based around a pragmatic outlook, with regard to the needs of the network administrator. The modularity of the design was important, due to the fast changing nature of the network device languages being processed. An object oriented approach was taken, for maximum changeability and extensibility, and a flexible tool was developed, due to the possible needs of different types users. System administrators desire, low level, CLI-based tools that they can trust, and use easily from scripting languages. Inexperienced users may prefer a more abstract, high level, GUI or Wizard that has an easier to learn process. Built around these ideas, the tool was implemented, and proved to be a usable, and complimentary addition to the many network policy-based systems currently available. The tool has a flexible design and contains comprehensive functionality. As opposed to some of the other tools which perform across multiple vendor languages, but do not implement a deep range of options for any of the languages. It compliments existing systems, such as policy compliance tools, and abstract policy analysis systems. Its validation algorithms were evaluated for both completeness, and performance. The tool was found to correctly process large firewall policies in just a few seconds. A framework for a policy-based management system, with which the tool would integrate, is also proposed. This is based around a vendor independent XML-based repository of device configurations, which could be used to bring together existing policy management and analysis systems.

Integrated magnetic components for high-power high-current dc-dc converters

This thesis is focused on the design and development of an integrated magnetic (IM) structure for use in high-power high-current power converters employed in renewable energy applications. These applications require low-cost, high efficiency and high-power density magnetic components and the use of IM structures can help achieve this goal. A novel CCTT-core split-winding integrated magnetic (CCTT IM) is presented in this thesis. This IM is optimized for use in high-power dc-dc converters. The CCTT IM design is an evolution of the traditional EE-core integrated magnetic (EE IM). The CCTT IM structure uses a split-winding configuration allowing for the reduction of external leakage inductance, which is a problem for many traditional IM designs, such as the EE IM. Magnetic poles are incorporated to help shape and contain the leakage flux within the core window. These magnetic poles have the added benefit of minimizing the winding power loss due to the airgap fringing flux as they shape the fringing flux away from the split-windings. A CCTT IM reluctance model is developed which uses fringing equations to accurately predict the most probable regions of fringing flux around the pole and winding sections of the device. This helps in the development of a more accurate model as it predicts the dc and ac inductance of the component. A CCTT IM design algorithm is developed which relies heavily on the reluctance model of the CCTT IM. The design algorithm is implemented using the mathematical software tool Mathematica. This algorithm is modular in structure and allows for the quick and easy design and prototyping of the CCTT IM. The algorithm allows for the investigation of the CCTT IM boxed volume with the variation of input current ripple, for different power ranges, magnetic materials and frequencies. A high-power 72 kW CCTT IM prototype is designed and developed for use in an automotive fuelcell-based drivetrain. The CCTT IM design algorithm is initially used to design the component while 3D and 2D finite element analysis (FEA) software is used to optimize the design. Low-cost and low-power loss ferrite 3C92 is used for its construction, and when combined with a low number of turns results in a very efficient design. A paper analysis is undertaken which compares the performance of the high-power CCTT IM design with that of two discrete inductors used in a two-phase (2L) interleaved converter. The 2L option consists of two discrete inductors constructed from high dc-bias material. Both topologies are designed for the same worst-case phase current ripple conditions and this ensures a like-for-like comparison. The comparison indicates that the total magnetic component boxed volume of both converters is similar while the CCTT IM has significantly lower power loss. Experimental results for the 72 kW, (155 V dc, 465 A dc input, 420 V dc output) prototype validate the CCTT IM concept where the component is shown to be 99.7 % efficient. The high-power experimental testing was conducted at General Motors advanced technology center in Torrence, Los Angeles. Calorific testing was used to determine the power loss in the CCTT IM component. Experimental 3.8 kW results and a 3.8 kW prototype compare and contrast the ferrite CCTT IM and high dc-bias 2L concepts over the typical operating range of a fuelcell under like-for-like conditions. The CCTT IM is shown to perform better than the 2L option over the entire power range. An 8 kW ferrite CCTT IM prototype is developed for use in photovoltaic (PV) applications. The CCTT IM is used in a boost pre-regulator as part of the PV power stage. The CCTT IM is compared with an industry standard 2L converter consisting of two discrete ferrite toroidal inductors. The magnetic components are compared for the same worst-case phase current ripple and the experimental testing is conducted over the operation of a PV panel. The prototype CCTT IM allows for a 50 % reduction in total boxed volume and mass in comparison to the baseline 2L option, while showing increased efficiency.

Surface Insulation Resistance Degradation and Electrochemical Migration on Printed Circuit Boards

Widespread adoption of lead-free materials and processing for printed circuit board (PCB) assembly has raised reliability concerns regarding surface insulation resistance (SIR) degradation and electrochemical migration (ECM). As PCB conductor spacings decrease, electronic products become more susceptible to these failures mechanisms, especially in the presence of surface contamination and flux residues which might remain after no-clean processing. Moreover, the probability of failure due to SIR degradation and ECM is affected by the interaction between physical factors (such as temperature, relative humidity, electric field) and chemical factors (such as solder alloy, substrate material, no-clean processing). Current industry standards for assessing SIR reliability are designed to serve as short-term qualification tests, typically lasting 72 to 168 hours, and do not provide a prediction of reliability in long-term applications. The risk of electrochemical migration with lead-free assemblies has not been adequately investigated. Furthermore, the mechanism of electrochemical migration is not completely understood. For example, the role of path formation has not been discussed in previous studies. Another issue is that there are very few studies on development of rapid assessment methodologies for characterizing materials such as solder flux with respect to their potential for promoting ECM. In this dissertation, the following research accomplishments are described: 1). Long-term temp-humidity-bias (THB) testing over 8,000 hours assessing the reliability of printed circuit boards processed with a variety of lead-free solder pastes, solder pad finishes, and substrates. 2). Identification of silver migration from Sn3.5Ag and Sn3.0Ag0.5Cu lead-free solder, which is a completely new finding compared with previous research. 3). Established the role of path formation as a step in the ECM process, and provided clarification of the sequence of individual steps in the mechanism of ECM: path formation, electrodeposition, ion transport, electrodeposition, and filament formation. 4). Developed appropriate accelerated testing conditions for assessing the no-clean processed PCBs' susceptibility to ECM: a). Conductor spacings in test structures should be reduced in order to reflect the trend of higher density electronics and the effect of path formation, independent of electric field, on the time-to-failure. b). THB testing temperatures should be modified according to the material present on the PCB, since testing at 85oC can cause the evaporation of weak organic acids (WOAs) in the flux residues, leading one to underestimate the risk of ECM. 5). Correlated temp-humidity-bias testing with ion chromatography analysis and potentiostat measurement to develop an efficient and effective assessment methodology to characterize the effect of no-clean processing on ECM.

Correlates of HIV testing among abused women in South Africa.

Gender-based violence increases a woman's risk for HIV but little is known about her decision to get tested. We interviewed 97 women seeking abuse-related services from a nongovernmental organization (NGO) in Johannesburg, South Africa. Forty-six women (47%) had been tested for HIV. Caring for children (odds ratio [OR] = 0.27, 95% confidence interval [CI] = [0.07, 1.00]) and conversing with partner about HIV (OR = 0.13, 95% CI = [0.02, 0.85]) decreased odds of testing. Stronger risk-reduction intentions (OR = 1.27, 95% CI = [1.01, 1.60]) and seeking help from police (OR = 5.51, 95% CI = [1.18, 25.76]) increased odds of testing. Providing safe access to integrated services and testing may increase testing in this population. Infection with HIV is highly prevalent in South Africa where an estimated 16.2% of adults between the ages of 15 and 49 have the virus. The necessary first step to stemming the spread of HIV and receiving life-saving treatment is learning one's HIV serostatus through testing. Many factors may contribute to someone's risk of HIV infection and many barriers may prevent testing. One factor that does both is gender-based violence.