Aplicação das FPAA na realização de sistemas de ordem fraccionária

Esta tese de dissertação tem como principal objetivo a implementação de controladores fracionários utilizando diapositivos analógicos FPAA (Field Programable Analog Array). Embora estes dispositivos já não sejam um tecnologia recente, não tiveram grande aceitação comercial, daí não ter sido grande a sua evolução nesta última década. Mas para a elaboração de alguns circuitos analógicos, nomeadamente filtros, amplificadores e mesmo controladores PID (Proporcional-Integrativo-Derivativo) analógicos torna-se numa ferramenta que pode facilitar o projeto e implementação. Para a realização deste estudo, utilizou-se a placa de desenvolvimento da Anadigm AN231K04-DVLP3 juntamente com o software disponibilizado pela mesma empresa, o AnadigmDesigner2. Para a simulação e observação dos resultados foi utilizada a DAQ (Data Acquisition) Hilink da Zelton juntamente com o software Matlab. De forma a testar a implementação dos controladores fracionários nas FPAA foram realizados alguns circuitos no software e enviados para a FPAA comparando os resultados obtidos na simulação com os visualizados no osciloscópio. Por último foi projetado um controlador PIlDm recorrendo aos métodos de aproximação inteira descritos neste documento implementados na FPAA recorrendo ao uso de filtros de primeira e segunda ordem.

Real-time context-aware network security policy enforcement system (RC-NSPES)

The major technical objectives of the RC-NSPES are to provide a framework for the concurrent operation of reactive and pro-active security functions to deliver efficient and optimised intrusion detection schemes as well as enhanced and highly correlated rule sets for more effective alerts management and root-cause analysis. The design and implementation of the RC-NSPES solution includes a number of innovative features in terms of real-time programmable embedded hardware (FPGA) deployment as well as in the integrated management station. These have been devised so as to deliver enhanced detection of attacks and contextualised alerts against threats that can arise from both the network layer and the application layer protocols. The resulting architecture represents an efficient and effective framework for the future deployment of network security systems.

A clocking technique with power savings in virtex-based pipelined designs

This paper presents the evaluation in power consumption of a clocking technique for pipelined designs. The technique shows a dynamic power consumption saving of around 30% over a conventional global clocking mechanism. The results were obtained from a series of experiments of a systolic circuit implemented in Virtex-II devices. The conversion from a global-clocked pipelined design to the proposed technique is straightforward, preserving the original datapath design. The savings can be used immediately either as a power reduction benefit or to increase the frequency of operation of a design for the same power consumption.

Observation in the MINOS far detector of the shadowing of cosmic rays by the sun and moon

The shadowing of cosmic ray primaries by the moon and sun was observed by the MINOS far detector at a depth of 2070 mwe using 83.54 million cosmic ray muons accumulated over 1857.91 live-days. The shadow of the moon was detected at the 5.6 sigma level and the shadow of the sun at the 3.8 sigma level using a log-likelihood search in celestial coordinates. The moon shadow was used to quantify the absolute astrophysical pointing of the detector to be 0.17 +/- 0.12 degrees. Hints of interplanetary magnetic field effects were observed in both the sun and moon shadow. Published by Elsevier B.V.

Identificação de cavidades naturais por meio de eletrorresistividade na região de São Pedro (SP)

The scope of this work is the study of natural cavities in gullies through geophysics. The studied area is located in the city of São Pedro (SP) more precisely in the gully of Tucunzinho. The historic of the area shows that, since the 60s there were problems with the high rate of erosion in the gully. In addition to increased erosion, there is the appearance of cavities inside responsible for rebates, aggravating the situation. Geophysical methods have been successfully applied in environmental studies since they are noninvasive, are fast and relatively inexpensive. In order to better understand the context of formation of the pipes in relation to local geology, three arrangements were compared for the method of Electrical Resistivity, Schlumberger, Wenner and Dipole-dipole. Then, it was possible to determine which one is the best for this type of study. According to the data obtained in the field, the Schlumberger array presents more consistent results in relation to the erosive context analyzed

Development of an experiment for ultrahigh-precision g-factor

Die vorliegende Arbeit befasst sich mit der Entwicklung und dem Aufbau eines Experiments zur hochpräzisen Bestimmung des g-Faktors gebundener Elektronen in hochgeladenen Ionen. Der g-Faktor eines Teilchens ist eine dimensionslose Konstante, die die Stärke der Wechselwirkung mit einem magnetischen Feld beschreibt. Im Falle eines an ein hochgeladenes Ion gebundenen Elektrons, dient es als einer der genausten Tests der Quantenelektrodynamik gebundener Zustande (BS-QED). Die Messung wird in einem dreifach Penning-Fallen System durchgeführt und basiert auf dem kontinuierlichen Stern-Gerlach-Effekt. Der erste Teil dieser Arbeit gibt den aktuellen Wissensstand über magnetische Momente wieder. Der hier gewählte experimentelle Aufbau wird begründet. Anschließend werden die experimentellen Anforderungen und die verwendeten Messtechniken erläutert. Das Ladungsbrüten der Ionen - einer der wichtigsten Aufgaben dieser Arbeit - ist dargestellt. Seine Realisierung basiert auf einer Feld-Emissions-Spitzen-Anordnung, die die Messung des Wirkungsquerschnitts für Elektronenstoßionisation ermöglicht. Der letzte Teil der Arbeit widmet sich der Entwicklung und dem Aufbau des Penning-Fallen Systems, sowie der Implementierung des Nachweisprozesses. Gegenwärtig ist der Aufbau zur Erzeugung hochgeladener Ionen und der dazugehörigen Messung des g-Faktors abgeschlossen, einschließlich des Steuerprogramms für die erste Datennahme. Die Ionenerzeugung und das Ladungsbrüten werden die nächsten Schritte sein.

Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs

Systems relying on fixed hardware components with a static level of parallelism can suffer from an underuse of logical resources, since they have to be designed for the worst-case scenario. This problem is especially important in video applications due to the emergence of new flexible standards, like Scalable Video Coding (SVC), which offer several levels of scalability. In this paper, Dynamic and Partial Reconfiguration (DPR) of modern FPGAs is used to achieve run-time variable parallelism, by using scalable architectures where the size can be adapted at run-time. Based on this proposal, a scalable Deblocking Filter core (DF), compliant with the H.264/AVC and SVC standards has been designed. This scalable DF allows run-time addition or removal of computational units working in parallel. Scalability is offered together with a scalable parallelization strategy at the macroblock (MB) level, such that when the size of the architecture changes, MB filtering order is modified accordingly

Thermal, stress, and traps effects in AlGaN/GaN HEMTs

GaN y AlN son materiales semiconductores piezoeléctricos del grupo III-V. La heterounión AlGaN/GaN presenta una elevada carga de polarización tanto piezoeléctrica como espontánea en la intercara, lo que genera en su cercanía un 2DEG de grandes concentración y movilidad. Este 2DEG produce una muy alta potencia de salida, que a su vez genera una elevada temperatura de red. Las tensiones de puerta y drenador provocan un stress piezoeléctrico inverso, que puede afectar a la carga de polarización piezoeléctrica y así influir la densidad 2DEG y las características de salida. Por tanto, la física del dispositivo es relevante para todos sus aspectos eléctricos, térmicos y mecánicos. En esta tesis se utiliza el software comercial COMSOL, basado en el método de elementos finitos (FEM), para simular el comportamiento integral electro-térmico, electro-mecánico y electro-térmico-mecánico de los HEMTs de GaN. Las partes de acoplamiento incluyen el modelo de deriva y difusión para el transporte electrónico, la conducción térmica y el efecto piezoeléctrico. Mediante simulaciones y algunas caracterizaciones experimentales de los dispositivos, hemos analizado los efectos térmicos, de deformación y de trampas. Se ha estudiado el impacto de la geometría del dispositivo en su auto-calentamiento mediante simulaciones electro-térmicas y algunas caracterizaciones eléctricas. Entre los resultados más sobresalientes, encontramos que para la misma potencia de salida la distancia entre los contactos de puerta y drenador influye en generación de calor en el canal, y así en su temperatura. El diamante posee une elevada conductividad térmica. Integrando el diamante en el dispositivo se puede dispersar el calor producido y así reducir el auto-calentamiento, al respecto de lo cual se han realizado diversas simulaciones electro-térmicas. Si la integración del diamante es en la parte superior del transistor, los factores determinantes para la capacidad disipadora son el espesor de la capa de diamante, su conductividad térmica y su distancia a la fuente de calor. Este procedimiento de disipación superior también puede reducir el impacto de la barrera térmica de intercara entre la capa adaptadora (buffer) y el substrato. La muy reducida conductividad eléctrica del diamante permite que pueda contactar directamente el metal de puerta (muy cercano a la fuente de calor), lo que resulta muy conveniente para reducir el auto-calentamiento del dispositivo con polarización pulsada. Por otra parte se simuló el dispositivo con diamante depositado en surcos atacados sobre el sustrato como caminos de disipación de calor (disipador posterior). Aquí aparece una competencia de factores que influyen en la capacidad de disipación, a saber, el surco atacado contribuye a aumentar la temperatura del dispositivo debido al pequeño tamaño del disipador, mientras que el diamante disminuiría esa temperatura gracias a su elevada conductividad térmica. Por tanto, se precisan capas de diamante relativamente gruesas para reducer ele efecto de auto-calentamiento. Se comparó la simulación de la deformación local en el borde de la puerta del lado cercano al drenador con estructuras de puerta estándar y con field plate, que podrían ser muy relevantes respecto a fallos mecánicos del dispositivo. Otras simulaciones se enfocaron al efecto de la deformación intrínseca de la capa de diamante en el comportamiento eléctrico del dispositivo. Se han comparado los resultados de las simulaciones de la deformación y las características eléctricas de salida con datos experimentales obtenidos por espectroscopía micro-Raman y medidas eléctricas, respectivamente. Los resultados muestran el stress intrínseco en la capa producido por la distribución no uniforme del 2DEG en el canal y la región de acceso. Además de aumentar la potencia de salida del dispositivo, la deformación intrínseca en la capa de diamante podría mejorar la fiabilidad del dispositivo modulando la deformación local en el borde de la puerta del lado del drenador. Finalmente, también se han simulado en este trabajo los efectos de trampas localizados en la superficie, el buffer y la barrera. Las medidas pulsadas muestran que tanto las puertas largas como las grandes separaciones entre los contactos de puerta y drenador aumentan el cociente entre la corriente pulsada frente a la corriente continua (lag ratio), es decir, disminuir el colapse de corriente (current collapse). Este efecto ha sido explicado mediante las simulaciones de los efectos de trampa de superficie. Por su parte, las referidas a trampas en el buffer se enfocaron en los efectos de atrapamiento dinámico, y su impacto en el auto-calentamiento del dispositivo. Se presenta también un modelo que describe el atrapamiento y liberación de trampas en la barrera: mientras que el atrapamiento se debe a un túnel directo del electrón desde el metal de puerta, el desatrapamiento consiste en la emisión del electrón en la banda de conducción mediante túnel asistido por fonones. El modelo también simula la corriente de puerta, debida a la emisión electrónica dependiente de la temperatura y el campo eléctrico. Además, también se ilustra la corriente de drenador dependiente de la temperatura y el campo eléctrico. ABSTRACT GaN and AlN are group III-V piezoelectric semiconductor materials. The AlGaN/GaN heterojunction presents large piezoelectric and spontaneous polarization charge at the interface, leading to high 2DEG density close to the interface. A high power output would be obtained due to the high 2DEG density and mobility, which leads to elevated lattice temperature. The gate and drain biases induce converse piezoelectric stress that can influence the piezoelectric polarization charge and further influence the 2DEG density and output characteristics. Therefore, the device physics is relevant to all the electrical, thermal, and mechanical aspects. In this dissertation, by using the commercial finite-element-method (FEM) software COMSOL, we achieved the GaN HEMTs simulation with electro-thermal, electro-mechanical, and electro-thermo-mechanical full coupling. The coupling parts include the drift-diffusion model for the electron transport, the thermal conduction, and the piezoelectric effect. By simulations and some experimental characterizations, we have studied the device thermal, stress, and traps effects described in the following. The device geometry impact on the self-heating was studied by electro-thermal simulations and electrical characterizations. Among the obtained interesting results, we found that, for same power output, the distance between the gate and drain contact can influence distribution of the heat generation in the channel and thus influence the channel temperature. Diamond possesses high thermal conductivity. Integrated diamond with the device can spread the generated heat and thus potentially reduce the device self-heating effect. Electro-thermal simulations on this topic were performed. For the diamond integration on top of the device (top-side heat spreading), the determinant factors for the heat spreading ability are the diamond thickness, its thermal conductivity, and its distance to the heat source. The top-side heat spreading can also reduce the impact of thermal boundary resistance between the buffer and the substrate on the device thermal behavior. The very low electrical conductivity of diamond allows that it can directly contact the gate metal (which is very close to the heat source), being quite convenient to reduce the self-heating for the device under pulsed bias. Also, the diamond coated in vias etched in the substrate as heat spreading path (back-side heat spreading) was simulated. A competing mechanism influences the heat spreading ability, i.e., the etched vias would increase the device temperature due to the reduced heat sink while the coated diamond would decrease the device temperature due to its higher thermal conductivity. Therefore, relative thick coated diamond is needed in order to reduce the self-heating effect. The simulated local stress at the gate edge of the drain side for the device with standard and field plate gate structure were compared, which would be relevant to the device mechanical failure. Other stress simulations focused on the intrinsic stress in the diamond capping layer impact on the device electrical behaviors. The simulated stress and electrical output characteristics were compared to experimental data obtained by micro-Raman spectroscopy and electrical characterization, respectively. Results showed that the intrinsic stress in the capping layer caused the non-uniform distribution of 2DEG in the channel and the access region. Besides the enhancement of the device power output, intrinsic stress in the capping layer can potentially improve the device reliability by modulating the local stress at the gate edge of the drain side. Finally, the surface, buffer, and barrier traps effects were simulated in this work. Pulsed measurements showed that long gates and distances between gate and drain contact can increase the gate lag ratio (decrease the current collapse). This was explained by simulations on the surface traps effect. The simulations on buffer traps effects focused on illustrating the dynamic trapping/detrapping in the buffer and the self-heating impact on the device transient drain current. A model was presented to describe the trapping and detrapping in the barrier. The trapping was the electron direct tunneling from the gate metal while the detrapping was the electron emission into the conduction band described by phonon-assisted tunneling. The reverse gate current was simulated based on this model, whose mechanism can be attributed to the temperature and electric field dependent electron emission in the barrier. Furthermore, the mechanism of the device bias via the self-heating and electric field impact on the electron emission and the transient drain current were also illustrated.

A Dynamically Adaptable Bus Architecture for Trading-Off Among Performance, Consumption and Dependability in Cyber-Physical Systems

Cyber-Physical Systems need to handle increasingly complex tasks, which additionally, may have variable operating conditions over time. Therefore, dynamic resource management to adapt the system to different needs is required. In this paper, a new bus-based architecture, called ARTICo3, which by means of Dynamic Partial Reconfiguration, allows the replication of hardware tasks to support module redundancy, multi-thread operation or dual-rail solutions for enhanced side-channel attack protection is presented. A configuration-aware data transaction unit permits data dispatching to more than one module in parallel, or provide coalesced data dispatching among different units to maximize the advantages of burst transactions. The selection of a given configuration is application independent but context-aware, which may be achieved by the combination of a multi-thread model similar to the CUDA kernel model specification, combined with a dynamic thread/task/kernel scheduler. A multi-kernel application for face recognition is used as an application example to show one scenario of the ARTICo3 architecture.

An Algorithm for Optimal Bipartite PLA Folding

This paper presents some results of PLA area optimizing by means of its column and row folding. A more restricted type of PLA simple folding is considered. It is introduced by Egan and Liu and called as bipartite folding. An efficient approach is presented which allows finding an optimal bipartite folding without exhaustive computational efforts.

Design for an IO block array in a tile-based FPGA

A design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.

Collimated Field Emission Beams from Metal Double-Gate Nanotip Arrays Optically Excited via Surface Plasmon Resonance

The generation of collimated electron beams from metal double-gate nanotip arrays excited by near infrared laser pulses is studied. Using electromagnetic and particle tracking simulations, we showed that electron pulses with small rms transverse velocities are efficiently produced from nanotip arrays by laser-induced field emission with the laser wavelength tuned to surface plasmon polariton resonance of the stacked double-gate structure. The result indicates the possibility of realizing a metal nanotip array cathode that outperforms state-of-the-art photocathodes.

Logic-gate devices based on printed polymer semiconducting nanostripes

The applications of organic semiconductors in complex circuitry such as printed CMOS-like logic circuits demand miniaturization of the active structures to the submicrometric and nanoscale level while enhancing or at least preserving the charge transport properties upon processing. Here, we addressed this issue by using a wet lithographic technique, which exploits and enhances the molecular order in polymers by spatial confinement, to fabricate ambipolar organic field effect transistors and inverter circuits based on nanostructured single component ambipolar polymeric semiconductor. In our devices, the current flows through a precisely defined array of nanostripes made of a highly ordered diketopyrrolopyrrole-benzothiadiazole copolymer with high charge carrier mobility (1.45 cm2 V-1 s-1 for electrons and 0.70 cm2 V-1 s-1 for holes). Finally, we demonstrated the functionality of the ambipolar nanostripe transistors by assembling them into an inverter circuit that exhibits a gain (105) comparable to inverters based on single crystal semiconductors.

Solution-processed dual-gate polymer field-effect transistors for display applications

We describe the advantages of dual-gate thin-film transistors (TFTs) for display applications. We show that in TFTs with active semiconductor layers composed of diketopyrrolopyrrole-naphthalene copolymer, the on-current is increased, the off-current is reduced, and the sub-threshold swing is improved compared to single-gate devices. Charge transport measurements in steady-state and under non-quasi-static conditions reveal the reasons for this improved performance. We show that in dual-gate devices, a much smaller fraction of charge carriers move in slow trap states. We also compare the activation energies for charge transport in the top-gate and bottom-gate configurations.

Enhancing field emission from a carbon nanotube array by lateral control of electrodynamic force field

Fluctuation of field emission current from carbon nanotubes (CNTs) poses certain difficulties for their use in nanobiomedical X-ray devices and imaging probes. This problem arises due to deformation of the CNTs due to electrodynamic force field and electron-phonon interaction. It is of great importance to have precise control of emitted electron beams very near the CNT tips. In this paper, a new array configuration with stacked array of CNTs is analysed and it is shown that the current density distribution is greatly localised at the middle of the array, that the scatter due to electrodynamic force field is minimised and that the temperature transients are much smaller compared to those in an array with random height distribution.