Coordination of Reactive Power in Grid-Connected Wind Farms for Voltage Stability Enhancement

This paper studies the feasibility of utilizing the reactive power of grid-connected variable-speed wind generators to enhance the steady-state voltage stability margin of the system. Allowing wind generators to work at maximum reactive power limit may cause the system to operate near the steady-state stability limit, which is undesirable. This necessitates proper coordination of reactive power output of wind generators with other reactive power controllers in the grid. This paper presents a trust region framework for coordinating reactive output of wind generators-with other reactive sources for voltage stability enhancement. Case studies on 418-bus equivalent system of Indian southern grid indicates the effectiveness of proposed methodology in enhancing the steady-state voltage stability margin.

On-line Estimation of Fundamental and Ripple Components of Line Currents in a Voltage-Source Inverter Operated at Low Switching Frequency

High-power voltage-source inverters (VSI) are often switched at low frequencies due to switching loss constraints. Numerous low-switching-frequency PWM techniques have been reported, which are quite successful in reducing the total harmonic distortion under open-loop conditions at such low operating frequencies. However, the line current still contains low-frequency components (though of reduced amplitudes), which are fed back to the current loop controller during closed-loop operation. Since the harmonic frequencies are quite low and are not much higher than the bandwidth of the current loop, these are amplified by the current controller, causing oscillations and instability. Hence, only the fundamental current should be fed back. Filtering out these harmonics from the measured current (before feeding back) leads to phase shift and attenuation of the fundamental component, while not eliminating the harmonics totally. This paper proposes a method for on-line extraction of the fundamental current in induction motor drives, modulated with low-switching-frequency PWM. The proposed method is validated through simulations on MATLAB/Simulink. Further, the proposed algorithm is implemented on Cyclone FPGA based controller board. Experimental results are presented for an R-L load.

Space vector based modulation scheme for reducing capacitor RMS current in three-level diode-clamped inverter

The DC capacitor is an important component in a voltage source inverter.The RMS current flowing through the capacitor determines the capacitor size and losses. The losses, in turn, influence the capacitor life. This paper proposes a space vector based modulation strategy for reducing the capacitor RMS current in a three-level diode-clamped inverter. An analytical closed-form expression is derived for the DC capacitor RMS current with the proposed PWM strategy. The analytical expression is validated through simulations and also experimentally. Theoretical and experimental results are presented, comparing the proposed strategy with conventional space vector PWM (CSVPWM). It is shown that the proposed strategy reduces the capacitor RMS current significantly at high modulation indices and high power factors. (C) 2014 Elsevier B.V. All rights reserved.

Small-Signal Stability Analysis of an Open-loop Induction Motor Drive Including the Effect of Inverter Dead-Time

This paper demonstrates light-load instability in open-loop induction motor drives on account of inverter dead-time. The dynamic equations of an inverter fed induction motor, incorporating the effect of dead-time, are considered. A procedure to derive the small-signal model of the motor, including the effect of inverter dead-time, is presented. Further, stability analysis is carried out on a 100-kW, 415V, 3-phase induction motor considering no-load. For voltage to frequency (i.e. V/f) ratios between 0.5 and 1 pu, the analysis brings out regions of instability on the V-f plane, in the frequency range between 5Hz and 20Hz. Simulation and experimental results show sub-harmonic oscillations in the motor current in this region, confirming instability as predicted by the analysis.

An Advanced Gate Driver for Insulated Gate Bipolar Transistors to Eliminate Dead-time Induced Distortions in Inverter Output

Dead-time is introduced between the gating signals to the top and bottom switches in a voltage source inverter (VSI) leg, to prevent shoot through fault due to the finite turn-off times of IGBTs. The dead-time results in a delay when the incoming device is an IGBT, resulting in error voltage pulses in the inverter output voltage. This paper presents the design, fabrication and testing of an advanced gate driver, which eliminates dead-time and consequent output distortion. Here, the gating pulses are generated such that the incoming IGBT transition is not delayed and shoot-through is also prevented. The various logic units of the driver card and fault tolerance of the driver are verified through extensive tests on different topologies such as chopper, half-bridge and full-bridge inverter, and also at different conditions of load. Experimental results demonstrate the improvement in the load current waveform quality with the proposed circuit, on account of elimination of dead-time.

Optimal Pulse Width Modulation of Voltage-Source Inverter fed Motor Drives with Relaxation of Quarter Wave Symmetry Condition

Optimal switching angles for minimization of total harmonic distortion of line current (I-THD) in a voltage source inverter are determined traditionally by imposing half-wave symmetry (HWS) and quarter-wave symmetry (QWS) conditions on the pulse width modulated waveform. This paper investigates optimal switching angles with QWS relaxed. Relaxing QWS expands the solution space and presents the possibility of improved solutions. The optimal solutions without QWS are shown here to outperform the optimal solutions with QWS over a range of modulation index (M) between 0.82 and 0.94 for a switching frequency to fundamental frequency ratio of 5. Theoretical and experimental results are presented on a 2.3kW induction motor drive.

Filter Configuration and PWM Method For Single Phase Inverters with Reduced Conducted EMI Noise

Electromagnetic Interference (EMI) noise is one of the major issues during the design of the grid-tied power converters. Presence of high dv/dt in Common Mode (CM) voltage, excites the parasitic capacitances and causes injection of narrow peaky current to ground. This results in high EMI noise level. A topology consisting of a single phase PWM-rectifier with LCL filter, utilising bipolar PWM method is proposed which reduces the EMI noise level by more than 30dB. This filter topology is shown to be insensitive to the switching delays between the legs of the inverter. The proposed topology eliminates high dv/dt from the dc-bus CM voltage by making it sinusoidal. Hence, the high frequency CM current injection to ground is minimized.

ADAPTATION OF MW LEVEL NATURAL GAS LEAN BURN ENGINE FOR PRODUCER GAS OPERATION A GRID CONNECTED POWER PLANT

Availability of producer gas engines at MW being limited necessitates to adapt engine from natural gas operation. The present work focus on the development of necessary kit for adapting a 12 cylinder lean burn turbo-charged natural gas engine rated at 900 kWe (Waukesha make VHP5904LTD) to operate on producer and set up an appropriate capacity biomass gasification system for grid linked power generation in Thailand. The overall plant configuration had fuel processing, drying, reactor, cooling and cleaning system, water treatment, engine generator and power evacuation. The overall project is designed for evacuation of 1.5 MWe power to the state grid and had 2 gasification system with the above configuration and 3 engines. Two gasification system each designed for about 1100 kg/hr of woody biomass was connected to the engine using a producer gas carburetor for the necessary Air to fuel ratio control. In the use of PG to fuel IC engines, it has been recognized that the engine response will differ as compared to the response with conventional fueled operation due to the differences in the thermo-physical properties of PG. On fuelling a conventional engine with PG, power de-rating can be expected due to the lower calorific value (LCV), lower adiabatic flame temperature (AFT) and the lower than unity product to reactant more ratio. Further the A/F ratio for producer gas is about 1/10th that of natural gas and requires a different carburetor for engine operation. The research involved in developing a carburetor for varying load conditions. The patented carburetor is based on area ratio control, consisting of a zero pressure regulator and a separate gas and air line along with a mixing zone. The 95 litre engine at 1000 rpm has an electrical efficiency of 33.5 % with a heat input of 2.62 MW. Each engine had two carburetors designed for producer gas flow each capable of handling about 1200 m3/hr in order to provide similar engine heat input at a lower conversion efficiency. Cold flow studies simulating the engine carburetion system results showed that the A/F was maintained in the range of 1.3 +/- 0.1 over the entire flow range. Initially, the gasification system was tested using woody biomass and the gas composition was found to be CO 15 +/- 1.5 % H-2 22 +/- 2% CH4 2.2 +/- 0.5 CO2 11.25 +/- 1.4 % and rest N-2, with the calorific value in the range of 5.0 MJ/kg. After initial trials on the engine to fine tune the control system and adjust various engine operating parameter a peak load of 800 kWe was achieved, while a stable operating conditions was found to be at 750 kWe which is nearly 85 % of the natural gas rating. The specific fuel consumption was found to be 0.9 kg of biomass per kWh.

Seventeen-Level Inverter Formed by Cascading Flying Capacitor and Floating Capacitor H-Bridges

A multilevel inverter for generating 17 voltage levels using a three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors has been proposed. Various aspects of the proposed inverter like capacitor voltage balancing have been presented in the present paper. Experimental results are presented to study the performance of the proposed converter. The stability of the capacitor balancing algorithm has been verified both during transients and steady-state operation. All the capacitors in this circuit can be balanced instantaneously by using one of the pole voltage combinations. Another advantage of this topology is its ability to generate all the voltages from a single dc-link power supply which enables back-to-back operation of converter. Also, the proposed inverter can be operated at all load power factors and modulation indices. Additional advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels. This configuration has very low dv/dt and common-mode voltage variation.

Experimental Study on Switching Characteristics of an Inverter Leg Consisting of IGBTs of Dissimilar Makes

Usually the top and bottom IGBT devices in an inverter leg are of the same make (i.e. from same manufacturer). At low power level, these two devices even may be contained in the same module. However at high power levels the top and bottom devices are in separate modules. Sometimes, in the event of device failure, device of particular make may be replaced by one of another make, but of same ratings (on account of non-availability of the original make). This paper investigates the effect of such intermixing of two different makes of high power IGBTs in an inverter leg on the switching characteristics. The switching transitions between IGBT and diode of similar make and those of IGBT and diode of dissimilar make are compared experimentally at various DC link voltages and currents. The comparisons are made in terms of, IGBT peak turn-on di/dt, IGBT peak turn-off di/dt, peak diode reverse recovery current (I-rr), peak IGBT voltage overshoot and switching energy losses.

Filter Configuration and PWM Method For Single-Phase Inverters With Reduced Conducted EMI Noise

Electromagnetic interference (EMI) noise is one of the major issues during design of grid-tied power converters. A novel LCL filter topology for a single-phase pulsewidth modulation (PWM) rectifier that makes use of bipolar PWM method is proposed for a single-phase to three-phase motor drive power converter. The proposed topology eliminates high dv/dt from the dc-bus common-mode (CM) voltage by making it sinusoidal. Hence, the high-frequency CM current injection to the ground and the motor-side CM current are minimized. The proposed filter configuration makes the system insensitive to circuit non-idealities such as mismatch in inductors values, unequal turn-on and turn-off delays, and dead-time mismatch between the inverter legs. Different variants of the filter topology are compared to establish the effectiveness of the proposed circuit. Experimental results based on the EMI measurement on the grid side and the CM current measurement on the motor side are presented for a 5-kW motor drive. It is shown that the proposed filter topology reduces the EMI noise level by about 35 dB.

A controller design method for 3 phase 4 wire grid connected VSI with LCL filter

Closed loop control of a grid connected VSI requires line current control and dc bus voltage control. The closed loop system comprising PR current controller and grid connected VSI with LCL filter is a higher order system. Closed loop control gain expressions are therefore difficult to obtain directly for such systems. In this work a simplified approach has been adopted to find current and voltage controller gain expressions for a 3 phase 4 wire grid connected VSI with LCL filter. The closed loop system considered here utilises PR current controller in natural reference frame and PI controller for dc bus voltage control. Asymptotic frequency response plot and gain bandwidth requirements of the system have been used for current control and voltage controller design. A simplified lower order model, derived for closed loop current control, is used for the dc bus voltage controller design. The adopted design method has been verified through experiments by comparison of the time domain response.

Small-Signal Stability Analysis of an Open-Loop Induction Motor Drive Including the Effect of Inverter Deadtime

This paper demonstrates light-load instability in a 100-kW open-loop induction motor drive on account of inverter deadtime. An improved small-signal model of an inverter-fed induction motor is proposed. This improved model is derived by linearizing the nonlinear dynamic equations of the motor, which include the inverter deadtime effect. Stability analysis is carried out on the 100-kW415-V three-phase induction motor considering no load. The analysis brings out the region of instability of this motor drive on the voltage versus frequency (V-f) plane. This region of light-load instability is found to expand with increase in inverter deadtime. Subharmonic oscillations of significant amplitude are observed in the steady-state simulated and measured current waveforms, at numerous operating points in the unstable region predicted, confirming the validity of the stability analysis. Furthermore, simulation and experimental results demonstrate that the proposed model is more accurate than an existing small-signal model in predicting the region of instability.

Reduced common-mode voltage operation of a new seven-level hybrid multilevel inverter topology with a single DC voltage source

In this study, analysis of extending the linear modulation range of a zero common-mode voltage (CMV) operated n-level inverter by allowing reduced CMV switching is presented. A new hybrid seven-level inverter topology with a single DC supply is also presented in this study and inverter operation for zero and reduced CMV is analysed. Each phase of the inverter is realised by cascading two three-level flying capacitor inverters with a half-bridge module in between. Proposed inverter topology is operated with zero CMV for modulation index <86% and is operated with a CMV magnitude of V-dc/18 to extend the modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilising the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology.