Diseño de cabezal de adquisición para biopotenciales

La monitorización del funcionamiento del corazón se realiza generalmente por medio del análisis de los potenciales de acción generados en las células responsables de la contracción y relajación de este órgano. El proceso de monitorización mencionado consta de diferentes partes. En primer lugar, se adquieren las señales asociadas a la actividad de las células cardíacas. La conexión entre el cuerpo humano y el sistema de acondicionamiento puede ser implementada mediante diferentes tipos de electrodos – de placa metálica, de succión, top-hat, entre otros. Antes de la adquisición la señal eléctrica recogida por los electrodos debe ser acondicionada de acuerdo a las especificaciones de la entrada de la tarjeta de adquisición de datos (DAQ o DAC). Básicamente, debe amplificar la señal de tal manera que se aproveche al máximo el rango dinámico del cuantificador. Las características de ruido del amplificador requerido deben ser diseñadas teniendo en cuenta que el ruido interno del amplificador no afecte a la interpretación del electrocardiograma original (ECG). Durante el diseño del amplificador se han tenido en cuenta varios requisitos. Deberá optimizarse ña relación señal a ruido (SNR) de la señal entre la señal del ECG y el ruido de cuantificación. Además, el nivel de la señal ECG a la entrada de la DAQ deberá alcanzar el máximo nivel del cuantificador. También, el ruido total a la entrada del cuantificador debe ser despreciable frente a la mínima señal discernible del ECG Con el objetivo de llevar a cabo un diseño electrónico con esas prestaciones de ruido, es necesario llevar a cabo un minucioso estudio de los fundamentos de caracterización de ruido. Se han abarcado temas como la teoría básica de señales aleatorias, análisis espectral y su aplicación a la caracterización en sistemas electrónicos. Finalmente, todos esos conceptos han sido aplicados a la caracterización de las diferentes fuentes de ruido en los circuitos con amplificadores operacionales. Muchos prototipos de amplificadores correspondientes a diferentes diseños han sido implementados en placas de circuito impreso (PCB – Printed Board Circuits). Aunque el ancho de banda del amplificador operacional es adecuado para su implementación en una ‘protoboard’, las especificaciones de ruido obligan al uso de PCB. De hecho, los circuitos implementados en PCB son menos sensibles al ruido e interferencias que las ‘protoboard’ dadas las características físicas de ambos tipos de prototipos.

Aplicación móvil para la gestión de los gastos en pisos compartidos

En esta memoria se describe el diseño y las pautas seguidas para la construcción de una aplicación móvil que permite la creación de grupos de personas para la gestión de los gastos, facturas y deudas comunitarias. Con un soporte Front-End en Android, un Back-End desarrollado en PHP y un almacenamiento de la información en una base de datos NoSQL, concretamente en MongoDB. El proyecto se ha realizado en grupo, separando los módulos Front-End y Back-End en dos proyectos distintos. En este proyecto desarrollamos el módulo Back-End. En él encontraremos el diseño para la construcción de la arquitectura REST y dar solución a la comunicación cliente y servidor de la aplicación. Además se ha añadido la componente PaaS (Platform as a Service) para acercar el desarrollo de este proyecto a un entorno de producción más real, afrontando así problemas reales. Al tratarse de un proyecto en equipo, el uso de metodologías ágiles cobra más importancia, por ello en este proyecto se ha hecho uso de la metodología Scrum.

Holistic Design In High-Speed Optical Interconnects

Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking.

In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy efficiency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The receiver sensitivity is measured to be -8.8dBm at 32Gb/s.

Next, on the optical transmitter side, three new techniques will be presented. First one is a differential ring modulator that breaks the optical bandwidth/quality factor trade-off known to limit the speed of high-Q ring modulators. This structure maintains a constant energy in the ring to avoid pattern-dependent power droop. As a first proof of concept, a prototype has been fabricated and measured up to 10Gb/s. The second technique is thermal stabilization of micro-ring resonator modulators through direct measurement of temperature using a monolithic PTAT temperature sensor. The measured temperature is used in a feedback loop to adjust the thermal tuner of the ring. A prototype is fabricated and a closed-loop feedback system is demonstrated to operate at 20Gb/s in the presence of temperature fluctuations. The third technique is a switched-capacitor based pre-emphasis technique designed to extend the inherently low bandwidth of carrier injection micro-ring modulators. A measured prototype of the optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit based on the monolithic PTAT sensor consumes 0.29mW.

Lastly, a first-order frequency synthesizer that is suitable for high-speed on-chip clock generation will be discussed. The proposed design features an architecture combining an LC quadrature VCO, two sample-and-holds, a PI, digital coarse-tuning, and rotational frequency detection for fine-tuning. In addition to an electrical reference clock, as an extra feature, the prototype chip is capable of receiving a low jitter optical reference clock generated by a high-repetition-rate mode-locked laser. The output clock at 8GHz has an integrated RMS jitter of 490fs, peak-to-peak periodic jitter of 2.06ps, and total RMS jitter of 680fs. The reference spurs are measured to be –64.3dB below the carrier frequency. At 8GHz the system consumes 2.49mW from a 1V supply.

Interdisciplinarity and Design Conceptualisation: Contributions from a Small-Scale Design Experiment

Literature emphasises the sparse research focused in collaborative and open approaches in the design conceptualisation stage, also known as the Fuzzy Front-End (FFE). Presently, the most challenging discussion arising from this specific field of research lies in understanding on whether or not to structure the referred conceptual stage. Accordingly, the established hypothesis behind this study sustains that a structured approach in the FFE would benefit the interdisciplinary dialogue. Therefore, two objectives support this study: to understand the benefits of an interdisciplinary approach in the FFE, and to test one proposed model for this conceptual stage. By means of a small-scale design experiment, this paper pretends to give additional contributions to this area of research, in the context of new product development (NPD). The general research supporting this specific study aims to conceptualise in the area of newly and futuristic aircraft configurations. Hence, this same topic based the conceptualisation process in the conducted ideation sessions, which are conducted by five different teams of three elements each. The results of the different ideation sessions reinforce the contemporary paradigm of Open Innovation (OI), which is based in trust and communication to better collaborate. The postulated hypothesis for this study is partially validated as teams testing the proposed and structured model generally consider that its usage would benefit the integration of different disciplines. Besides, a general feeling that a structured approach integrates different perspectives and gives creativity a focus pervades. Nevertheless, the small-scale of the design experiment attributes some limitations to this study, despite giving new insights in how to better organise coming and more sustained studies. Interestingly, the importance of sketching as an interdisciplinary means of communication is underlined with the obtained results.

Radiation characteristics enhancement of planar structures using metasurfaces

In this thesis, the focus is on utilizing metasurfaces to improve radiation characteristics of planar structures. The study encompasses various aspects of metasurface applications, including enhancing antenna radiation characteristics and manipulating electromagnetic (EM) waves, such as polarization conversion and anomalous reflection. The thesis introduces the design of a single-port antenna with dual-mode operation, integrating metasurfaces. This antenna serves as the front-end for a next-generation tag, functioning as a position sensor with identification and energy harvesting capabilities. It operates in the lower European Ultra-Wideband (UWB) frequency range for communication/localization and the UHF band for wireless energy reception. The design aims for a low-profile stack-up that remains unaffected by background materials. Researchers worldwide are drawn to metasurfaces due to their EM wave manipulation capabilities. The thesis also demonstrates how a High-Impedance Surface (HIS) can enhance the antenna's versatility through metasurface application, including conformal design using 3D-printing technology, ensuring adaptability for various deformation and tracking/powering scenarios. Additionally, the thesis explores two distinct metasurface applications. One involves designing an angularly stable super-wideband Circular Polarization Converter (CPC) operating from 11 to 35GHz with an impressive relative impedance bandwidth of 104.3%. The CPC shows a stable response even at oblique incidences up to 40 degrees, with a Peak Cross-Polarization Ratio (PCR) exceeding 62% across the entire band. The second application focuses on an Intelligent Reflective Surface (IRS) capable of redirecting incoming waves in unconventional directions. Tunability is achieved through an artificially developed ferroelectric material (HfZrO) and distributed capacitive elements (IDC) to fine-tune impedance and phase responses at the meta-atom level. The IRS demonstrates anomalous reflection for normal incident waves. These innovative applications of metasurfaces offer promising advancements in antenna design, EM wave manipulation, and versatile wireless communication systems.

Progettazione di un sistema di business intelligence per offerwall incentivati

Lo scopo del presente elaborato è ottenere dati grezzi dai maggiori offerwalls affinché si renda possibile elaborarli ed analizzarli per metterli a disposizione delle figure che si occupano di account management di un potenziale Ad Network quale è MyAppFree. Il primo Ad Network competitor a venire integrato nel presente tool di Business Intelligence è OfferToro, seguito da AdGem, il quale è attualmente in fase di integrazione. Prima di presentare i risultati del tool, a cui è stato dedicato l’ultimo capitolo dell’elaborato, sono stati approfonditi ed analizzati ampiamente i concetti fondamentali per la comprensione del progetto insieme agli strumenti utilizzati per la costituzione dell’architettura software. Successivamente, viene presentata l'architettura dei singoli microservizi oltre a quella sistemistica generale, la quale tratta come le parti che compongono iBiT, interagiscono tra loro. Infine, l’ultima parte della trattazione è dedicata al funzionamento del Front End Side per la figura account manager, che rappresenta l’utente finale del progetto. Unita alle analisi dei risultati ottenuti tramite una fase di benchmark testing, metrica che misura un insieme ripetibile di risultati quantificabili che serve come punto di riferimento perché prodotti e servizi possano essere confrontati. Lo scopo dei risultati dei test di benchmark è quello di confrontare le versioni presenti e future del software tramite i rispettivi benchmark.

Calibration of the detector flight models for the HERMES and SPIRIT nanosatellite missions

The High Energy Rapid Modular Ensemble of Satellites (HERMES) is a new mission concept involving the development of a constellation of six CubeSats in low Earth orbit with new miniaturized instruments that host a hybrid Silicon Drift Detector/GAGG:Ce based system for X-ray and γ-ray detection, aiming to monitor high-energy cosmic transients, such as Gamma Ray Bursts and the electromagnetic counterparts of gravitational wave events. The HERMES constellation will also operate together with the Australian-Italian SpIRIT mission, which will house a HERMES-like detector. The HERMES pathfinder mini-constellation, consisting of six satellites plus SpIRIT, is likely to be launched in 2023. The HERMES detectors are based on the heritage of the Italian ReDSoX collaboration, with joint design and production by INFN-Trieste and Fondazione Bruno Kessler, and the involvement of several Italian research institutes and universities. An application-specific, low-noise, low-power integrated circuit (ASIC) called LYRA was conceived and designed for the HERMES readout electronics. My thesis project focuses on the ground calibrations of the first HERMES and SpIRIT flight detectors, with a performance assessment and characterization of the detectors. The first part of this work addresses measurements and experimental tests on laboratory prototypes of the HERMES detectors and their front-end electronics, while the second part is based on the design of the experimental setup for flight detector calibrations and related functional tests for data acquisition, as well as the development of the calibration software. In more detail, the calibration parameters (such as the gain of each detector channel) are determined using measurements with radioactive sources, performed at different operating temperatures between -20°C and +20°C by placing the detector in a suitable climate chamber. The final part of the thesis involves the analysis of the calibration data and a discussion of the results.

CartBot: un’applicazione di chat bot mobile per l’e-grocery

Sempre più negli ultimi anni si interagisce con i chatbot, software che simulano una conversazione con un essere umano utilizzando il linguaggio naturale. L’elaborato di tesi mira ad uno studio più approfondito della tematica, a partire da come tale tecnologia si è evoluta nel corso degli anni. Si procede analizzando le principali applicazioni dei bot, soffermandosi anche sui cambiamenti apportati dalla pandemia di Covid-19, ed evidenziando le principali ragioni che portano aziende e singoli al loro utilizzo. Inoltre, vengono descritti i diversi tipi di bot esistenti e viene analizzato il Natural Language Processing, ramo dell’Intelligenza Artificiale che mira alla comprensione del linguaggio naturale. Nei capitoli successivi viene descritto il progetto CartBot, un’applicazione di chat mobile per l’e-grocery, implementata come un chatbot che guida il cliente all’acquisto della spesa online. Vengono descritte le tecnologie utilizzate, con particolare riferimento al software di Google Dialogflow, che permette di sviluppare bot; inoltre viene analizzata come è stata effettuata la progettazione, sia lato front-end che back-end, allegando il flowchart, un diagramma di flusso realizzato per definire la sequenza di azioni e passaggi richiesti dal bot per effettuare l’acquisto. Infine, sono descritte le varie sottosezioni di CartBot, che riguardano la visualizzazione dei prodotti e il completamento dell’ordine, allegando screenshot dell’interfaccia finale ottenuta e inserendo il codice di alcune funzioni rilevanti.

SiC Multilayer Structures as Light Controlled Photonic Active Filters

Tunable wavelength division multiplexing converters based on amorphous SiC multilayer photonic active filters are analyzed. The configuration includes two stacked p-i-n structures (p(a-SiC:H)-i'(a-SiC:H)-n(a-SiC:H)-p(a-SiC:H)-i(a-Si:H)-n(a-Si:H)) sandwiched between two transparent contacts. The manipulation of the magnitude is achieved through appropriated front and back backgrounds. Transfer function characteristics are studied both theoretically and experimentally. An algorithm to decode the multiplex signal is established. An optoelectronic model supports the optoelectronic logic architecture. Results show that the light-activated device combines the demultiplexing operation with the simultaneous photodetection and self-amplification of an optical signal. The output waveform presents a nonlinear amplitude-dependent response to the wavelengths of the input channels. Depending on the wavelength of the external background and irradiation side, it acts either as a short- or a long-pass band filter or as a band-stop filter. A two-stage active circuit is presented and gives insight into the physics of the device.

Experimental validation of a proposed single-phase five-level active rectifier operating with model predictive current control

This paper presents a model predictive current control applied to a proposed single-phase five-level active rectifier (FLAR). This current control strategy uses the discrete-time nature of the active rectifier to define its state in each sampling interval. Although the switching frequency is not constant, this current control strategy allows to follow the reference with low total harmonic distortion (THDF). The implementation of the active rectifier that was used to obtain the experimental results is described in detail along the paper, presenting the circuit topology, the principle of operation, the power theory, and the current control strategy. The experimental results confirm the robustness and good performance (with low current THDF and controlled output voltage) of the proposed single-phase FLAR operating with model predictive current control.

A 2kW interleaved ZCS-FM boost rectifier digitally controlled by FPGA device

This paper presents a 2kW single-phase high power factor boost rectifier with four cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by Field Programmable Gate Array (FPGA). The soft-switching technique Is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-voltage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related 'to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the Interleaving technique, the rectifer's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) In the input current, in compliance with the TEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for four interleaved cells, and a closed-loop to provide the output voltage regulation, like as a pre-regulator rectifier. Experimental results are presented for a 2kW implemented prototype with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.

A multi-cell variable frequency interleaved ZCS boost rectifier digitally controlled by FPGA

This paper presents a multi-cell single-phase high power factor boost rectifier in interleave connection, operating in critical conduction mode, employing a soft-switching technique, and controlled by Field Programmable Gate Array (FPGA). The soft-switching technique is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-vohage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the interleaving technique, the rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the IEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for all interleaved cells, and a closed-loop to provide the output voltage regulation, like as a preregulator rectifier. Experimental results are presented for a implemented prototype with two and with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.