Injection barrier induced deviations in space charge limited conduction in doped poly(3-methylthiophene) based devices

The carrier density dependent current-voltage (J V) characteristics of electrochemically prepared poly(3-methylthiophene) (P3MeT) have been investigated in Pt/P3MeT/Al devices, as a function of temperature from 280 to 84 K. In these devices, the charge transport is found to be mainly governed by different transport regimes of space charge limited conduction (SCLC). In a lightly doped device, SCLC controlled by exponentially distributed traps (Vl+1 law, l > 1) is observed in the intermediate voltage range (0.5-2 V) at all temperatures. However, at higher bias (> 2 V), the current deviates from the usual Vl+1 law where the slope is found to be less than 2 of the logJ-logV plot, which is attributed to the presence of the injection barrier. These deviations gradually disappear at higher doping level due to reduction in the injection barrier. Numerical simulations of the Vl+1 law by introducing the injection barrier show good agreement with experimental data. The results show that carrier density can tune the charge transport mechanism in Pt/P3MeT/Al devices to understand the non-Ohmic behavior. The plausible reasons for the origin of injection barrier and the transitions in the transport mechanism with carrier density are discussed. (C) 2015 AIP Publishing LLC.

Tunability of 1/f Noise at Multiple Dirac Cones in hBN Encapsulated Graphene Devices

The emergence of multiple Dirac cones in hexagonal boron nitride (hBN)-graphene heterostructures is particularly attractive because it offers potentially better landscape for higher and versatile transport properties than the primary Dirac cone. However, the transport coefficients of the cloned Dirac cones is yet not fully characterized and many open questions, including the evolution of charge dynamics and impurity scattering responsible for them, have remained unexplored. Noise measurements, having the potential to address these questions, have not been performed to date in dual-gated hBN graphene hBN devices. Here, we present the low frequency 1/f noise measurements at multiple Dirac cones in hBN encapsulated single and bilayer graphene in dual-gated geometry. Our results reveal that the low-frequency noise in graphene can be tuned by more than two-orders of magnitude by changing carrier concentration as well as by modifying the band structure in bilayer graphene. We find that the noise is surprisingly suppressed at the cloned Dirac cone compared to the primary Dirac cone in single layer graphene device, while it is strongly enhanced for the bilayer graphene with band gap opening. The results are explained with the calculation of dielectric function using tight-binding model. Our results also indicate that the 1/f noise indeed follows the Hooge's empirical formula in hBN-protected devices in dual-gated geometry. We also present for the first time the noise data in bipolar regime of a graphene device.

Accelerating method of moments based package-board 3D parasitic extraction using FPGA

In this article, a Field Programmable Gate Array (FPGA)-based hardware accelerator for 3D electromagnetic extraction, using Method of Moments (MoM) is presented. As the number of nets or ports in a system increases, leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products presents a time bottleneck in a linear-complexity fast solver framework. In this work, an FPGA-based hardware implementation is proposed toward a two-level parallelization scheme: (i) matrix level parallelization for single RHS and (ii) pipelining for multiple-RHS. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple nets in a Ball Grid Array (BGA) package. The acceleration is shown to be linearly scalable with FPGA resources and speed-ups over 10x against equivalent software implementation on a 2.4GHz Intel Core i5 processor is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board with the implemented design operating at 200MHz clock frequency. (c) 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:776-783, 2016

All Inorganic Spin-Coated Nanoparticle-Based Capacitive Memory Devices

We demonstrate all inorganic, robust, cost-effective, spin-coated, two-terminal capacitive memory metal-oxide nanoparticle-oxide-semiconductor devices with cadmium telluride nanoparticles sandwiched between aluminum oxide phosphate layers to form the dielectric memory stack. Using a novel high-speed circuit to decouple reading and writing, experimentally measured memory windows, programming voltages, retention times, and endurance are comparable with or better than the two-terminal memory devices realized using other fabrication techniques.

Biological application of multi-component nanowires in hybrid devices powered by F-1-ATPase motors

In this paper, construction of hybrid device by integrating nanowires with F1-ATPase motors is described. The nickel nanowires and multi-segment nanowires, including gold and nickel, were fabricated by electrochemical deposition in nanoporous templates. The nickel nanowires functionalized by biotinylated peptide can be assembled directly onto F1-ATPase motors to act as the propellers. If the multicomponent nanowires, including gold and nickel, were selectively functionalized by the thiol group modified ssDNA and the synthetic peptide, respectively, the biotinylated F1- ATPase motors can be attached to the biotinylated peptide on nickel segment of the nanowires. Then, the multi-component nanowires can also be used as the propellers, and one may observe the rotations of the multi-component nanowires driven by F1-ATPase motors. Therefore, introduction of multiple segments along the length of a nanowire can lead to a variety of multiple chemical functionalities, which can be selectively bound to cells and special biomolecules. This method provides an insight for the construction of other hybrid devices with its controlling arrangement of different biomolecule on designed nanometer scale structures.

Zinc oxide nanowire networks for macroelectronic devices

Highly transparent zinc oxide (ZnO) nanowire networks have been used as the active material in thin film transistors (TFTs) and complementary inverter devices. A systematic study on a range of networks of variable density and TFT channel length was performed. ZnO nanowire networks provide a less lithographically intense alternative to individual nanowire devices, are always semiconducting, and yield significantly higher mobilites than those achieved from currently used amorphous Si and organic TFTs. These results suggest that ZnO nanowire networks could be ideal for inexpensive large area electronics. © 2009 American Institute of Physics.