436 resultados para Eutectic Solder


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Mg-8Gd-0.6Zr-xNd-yY (mass%) alloys which containing different Nd:Y mass ratio of 3:0, 2:1, 1:2 and 0:3 with a constant x + y = 3 were prepared by metal mould casting method, and the microstructure, aging behaviour and tensile properties have been investigated. The fibrous eutectic areas along the boundaries enlarge clearly in the as-cast alloys containing Y element, and the fine grain boundaries and dispersed precipitation are observed in the aged alloys. The Mg-8Gd-0.6Zr-2Nd-Y alloy exhibits notably age-hardening behaviour and the highest mechanical property. The ultimate tensile strength and yield strength of Mg-8Gd-0.6Zr-2Nd-Y alloy in the peak aged hardness are 293 and 221 MPa at room temperature, 248 and 191 MPa at 230 degrees C. The improvement of age-hardening response and tensile properties is mainly attributed to the quadrate-like stable Mg5RE precipitate, which forms readily and orderly in aged Mg-8Gd-0.6Zr-2Nd-Y alloy.

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In order to avoid the hygroscopicity of LiCl specimem, the method of directly chlorinating Li_2CO_3 with NH_4Cl was successfully introducing into the thermal analysis of the system containing LiCl. The three fusibility diagram of LiCl-KCl, LiClNaCl, LiCl-LiF were determined using the method. The results are in agreement wish the values reported in the literature, and phase diagram of LiCl-KCl-LiF ternary system was constructed based on these results. Temperature of the ternary eutectic, composed of 57.3mol%...

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This article describes Yasmina Khadra’s autobiographical work composed of two books: "L’écrivain" and "L’imposture des mots" and its reception in France. The main purpose of this study was to establish the literary genre of these books, which implies determining whether Khandra’s work represents an autobiography or an autofiction with reference to P. Lejeune’s and V. Colonna’s theoretical studies. The dividing line between two genres in Khandra’s works refl ects his inner split between being either a solder or a writer. The presentation will also help to understand the controversy resulting from Khandra’s participation in Algerian civil war. Moreover the analysis is related to modern Algerian history.

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The performance of an RF output matching network is dependent on integrity of the ground connection. If this connection is compromised in anyway, additional parasitic elements may occur that can degrade performance and yield unreliable results. Traditionally, designers measure Constant Wave (CW) power to determine that the RF chain is performing optimally, the device is properly matched and by implication grounded. It is shown that there are situations where modulation quality can be compromised due to poor grounding that is not apparent using CW power measurements alone. The consequence of this is reduced throughput, range and reliability. Measurements are presented on a Tyndall Mote using a CC2420 RFIC todemonstrate how poor solder contact between the ground contacts and the ground layer of the PCB can lead tothe degradation of modulated performance. Detailed evaluation that required the development of a new measurement definition for 802.15.4 and analysis is presented to show how waveform quality is affected while the modulated output power remains within acceptable limits.

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This article describes feasible and improved ways towards enhanced nanowire growth kinetics by reducing the equilibrium solute concentration in the liquid collector phase in a vapor-liquid-solid (VLS) like growth model. Use of bi-metallic alloy seeds (AuxAg1-x) influences the germanium supersaturation for a faster nucleation and growth kinetics. Nanowire growth with ternary eutectic alloys shows Gibbs-Thompson effect with diameter dependent growth rate. In-situ transmission electron microscopy (TEM) annealing experiments directly confirms the role of equilibrium concentration in nanowire growth kinetics and was used to correlate the equilibrium content of metastable alloys with the growth kinetics of Ge nanowires. The shape and geometry of the heterogeneous interfaces between the liquid eutectic and solid Ge nanowires were found to vary as a function of nanowire diameter and eutectic alloy composition.

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Widespread adoption of lead-free materials and processing for printed circuit board (PCB) assembly has raised reliability concerns regarding surface insulation resistance (SIR) degradation and electrochemical migration (ECM). As PCB conductor spacings decrease, electronic products become more susceptible to these failures mechanisms, especially in the presence of surface contamination and flux residues which might remain after no-clean processing. Moreover, the probability of failure due to SIR degradation and ECM is affected by the interaction between physical factors (such as temperature, relative humidity, electric field) and chemical factors (such as solder alloy, substrate material, no-clean processing). Current industry standards for assessing SIR reliability are designed to serve as short-term qualification tests, typically lasting 72 to 168 hours, and do not provide a prediction of reliability in long-term applications. The risk of electrochemical migration with lead-free assemblies has not been adequately investigated. Furthermore, the mechanism of electrochemical migration is not completely understood. For example, the role of path formation has not been discussed in previous studies. Another issue is that there are very few studies on development of rapid assessment methodologies for characterizing materials such as solder flux with respect to their potential for promoting ECM. In this dissertation, the following research accomplishments are described: 1). Long-term temp-humidity-bias (THB) testing over 8,000 hours assessing the reliability of printed circuit boards processed with a variety of lead-free solder pastes, solder pad finishes, and substrates. 2). Identification of silver migration from Sn3.5Ag and Sn3.0Ag0.5Cu lead-free solder, which is a completely new finding compared with previous research. 3). Established the role of path formation as a step in the ECM process, and provided clarification of the sequence of individual steps in the mechanism of ECM: path formation, electrodeposition, ion transport, electrodeposition, and filament formation. 4). Developed appropriate accelerated testing conditions for assessing the no-clean processed PCBs' susceptibility to ECM: a). Conductor spacings in test structures should be reduced in order to reflect the trend of higher density electronics and the effect of path formation, independent of electric field, on the time-to-failure. b). THB testing temperatures should be modified according to the material present on the PCB, since testing at 85oC can cause the evaporation of weak organic acids (WOAs) in the flux residues, leading one to underestimate the risk of ECM. 5). Correlated temp-humidity-bias testing with ion chromatography analysis and potentiostat measurement to develop an efficient and effective assessment methodology to characterize the effect of no-clean processing on ECM.

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This paper describes how modeling technology has been used in providing fatigue life time data of two flip-chip models. Full-scale three-dimensional modeling of flip-chips under cyclic thermal loading has been combined with solder joint stand-off height prediction to analyze the stress and strain conditions in the two models. The Coffin-Manson empirical relationship is employed to predict the fatigue life times of the solder interconnects. In order to help designers in selecting the underfill material and the printed circuit board, the Young's modulus and the coefficient of thermal expansion of the underfill, as well as the thickness of the printed circuit boards are treated as variable parameters. Fatigue life times are therefore calculated over a range of these material and geometry parameters. In this paper we will also describe how the use of micro-via technology may affect fatigue life

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Surface tension induced flow is implemented into a numerical modelling framework and validated for a number of test cases. Finite volume unstructured mesh techniques are used to discretize the mass, momentum and energy conservation equations in three dimensions. An explicit approach is used to include the effect of surface tension forces on the flow profile and final shape of a liquid domain. Validation of this approach is made against both analytical and experimental data. Finally, the method is used to model the wetting balance test for solder alloy material, where model predictions are used to gain a greater insight into this process. Copyright © 2000 John Wiley & Sons, Ltd.

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A flip chip component is a silicon chip mounted to a substrate with the active area facing the substrate. This paper presents the results of an investigation into the relationship between a number of important material properties and geometric parameters on the thermal-mechanical fatigue reliability of a standard flip chip design and a flip chip design with the use of microvias. Computer modeling has been used to analyze the mechanical conditions of flip chips under cyclic thermal loading where the Coffin-Manson empirical relationship has been used to predict the life time of the solder interconnects. The material properties and geometry parameters that have been investigated are the Young's modulus, the coefficient of thermal expansion (CTE) of the underfill, the out-of-plane CTE (CTEz) of the substrate, the thickness of the substrate, and the standoff height. When these parameters vary, the predicted life-times are calculated and some of the features of the results are explained. By comparing the predicted lifetimes of the two designs and the strain conditions under thermal loading, the local CTE mismatch has been found to be one of most important factors in defining the reliability of flip chips with microvias.

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This paper describes modelling technology and its use in providing data governing the assembly of flip-chip components. Details are given on the reflow and curing stages as well as the prediction of solder joint shapes. The reflow process involves the attachment of a die to a board via solder joints. After a reflow process, underfill material is placed between the die and the substrate where it is heated and cured. Upon cooling the thermal mismatch between the die, underfill, solder bumps, and substrate will result in a nonuniform deformation profile across the assembly and hence stress. Shape predictions then thermal solidification and stress prediction are undertaken on solder joints during the reflow process. Both thermal and stress calculations are undertaken to predict phenomena occurring during the curing of the underfill material. These stresses may result in delamination between the underfill and its surrounding materials leading to a subsequent reduction in component performance and lifetime. Comparisons between simulations and experiments for die curvature will be given for the reflow and curing process

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This paper describes the application of computational fluid dynamics (CFD) to simulate the macroscopic bulk motion of solder paste ahead of a moving squeegee blade in the stencil printing process during the manufacture of electronic components. The successful outcome of the stencil printing process is dependent on the interaction of numerous process parameters. A better understanding of these parameters is required to determine their relation to print quality and improve guidelines for process optimization. Various modelling techniques have arisen to analyse the flow behaviour of solder paste, including macroscopic studies of the whole mass of paste as well as microstructural analyses of the motion of individual solder particles suspended in the carrier fluid. This work builds on the knowledge gained to date from earlier analytical models and CFD investigations by considering the important non-Newtonian rheological properties of solder pastes which have been neglected in previous macroscopic studies. Pressure and velocity distributions are obtained from both Newtonian and non-Newtonian CFD simulations and evaluated against each other as well as existing established analytical models. Significant differences between the results are observed, which demonstrate the importance of modelling non-Newtonian properties for realistic representation of the flow behaviour of solder paste.

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The liquid metal flow in induction crucible models is known to be unstable, turbulent and difficult to predict in the regime of medium frequencies when the electromagnetic skin-layer is of considerable extent. We present long term turbulent flow measurements by a permanent magnet incorporated potential difference velocity probe in a cylindrical container filled with eutectic melt In-Ga-Sn. The parallel numerical simulation of the long time scale development of the turbulent average flow is presented. The numerical flow model uses an implicit pseudo-spectral code and k-w turbulence model, which was recently developed for the transitional flow modelling. The results compare reasonably to the experiment and demonstrate the time development of the turbulent flow field and the turbulence energy.

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This paper demonstrates a modeling and design approach that couples computational mechanics techniques with numerical optimisation and statistical models for virtual prototyping and testing in different application areas concerning reliability of eletronic packages. The integrated software modules provide a design engineer in the electronic manufacturing sector with fast design and process solutions by optimizing key parameters and taking into account complexity of certain operational conditions. The integrated modeling framework is obtained by coupling the multi-phsyics finite element framework - PHYSICA - with the numerical optimisation tool - VisualDOC into a fully automated design tool for solutions of electronic packaging problems. Response Surface Modeling Methodolgy and Design of Experiments statistical tools plus numerical optimisaiton techniques are demonstrated as a part of the modeling framework. Two different problems are discussed and solved using the integrated numerical FEM-Optimisation tool. First, an example of thermal management of an electronic package on a board is illustrated. Location of the device is optimized to ensure reduced junction temperature and stress in the die subject to certain cooling air profile and other heat dissipating active components. In the second example thermo-mechanical simulations of solder creep deformations are presented to predict flip-chip reliability and subsequently used to optimise the life-time of solder interconnects under thermal cycling.

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Experiments as well as computer modeling methods have been used to investigate the effect of the solder reflow process on the electrical characteristics and reliability of anisotropic conductive film (ACF) interconnections. In the experiments, the contact resistance of the ACF interconnections was found to increase after a subsequent reflow and the magnitude of this increase was strongly correlated to the peak temperature of the reflow profile. In fact, nearly 40 percent of the joints were opened (i.e. lifted away from the pad) after the reflow with a peak temperature of 260 OC while no openings was observed when the peak temperature was 210 "C. It is believed that the CTE mismatch between the polymer particle and the adhesive matrix is the main cause of this contact degradation. To understand this phenomenon better, a 3-D model of an ACF joint structure was built and Finite Element Analysis was used to predict the stress distrihution in the conductive particles, adhesive matrix and metal pads during the reflow process. The effects of the peak temperature, the CTE of the adhesive matrix and the bump height on the reliability of the ACF interconnections were discussed.

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Traditionally, before flip chips can be assembled the dies have to be attached with solder bumps. This process involves the deposition of metal layers on the Al pads on the dies and this is called the under bump metallurgy (UBM). In an alternative process, however, Copper (Cu) columns can be used to replace solder bumps and the UBM process may be omitted altogether. After the bumping process, the bumped dies can be assembled on to the printed circuit board (PCB) by using either solder or conductive adhesives. In this work, the reliability issues of flip chips with Cu column bumped dies have been studied. The flip chip lifetime associated with the solder fatigue failure has been modeled for a range of geometric parameters. The relative importance of these parameters is given and solder volume has been identified as the most important design parameter for long-term reliability. Another important problem that has been studied in this work is the dissolution of protection metals on the pad and Cu column in the reflow process. For small solder joints the amount of Cu which dissolves into the molten solder after the protection layers have worn out may significantly affect solder joint properties.