Equivalent Model Of Expansion Of Cement Mortar Under Sulphate Erosion

The expansion property of cement mortar under the attack of sulfate ions is studied by experimental and theoretical methods. First, cement mortars are fabricated with the ratio of water to cement of 0.4, 0.6, and 0.8. Secondly, the expansion of specimen immerged in sulphate solution is measured at different times. Thirdly, a theoretical model of expansion of cement mortar under sulphate erosion is suggested by virtue of represent volume element method. In this model, the damage evolution due to the interaction between delayed ettringite and cement mortar is taken into account. Finally, the numerical calculation is performed. The numerical and experimental results indicate that the model perfectly describes the expansion of the cement mortar.

EQUIVALENT MODEL OF EXPANSION OF CEMENT MORTAR UNDER SULPHATE EROSION

The expansion property of cement mortar under the attack of sulfate ions is studied by experimental and theoretical methods. First, cement mortars are fabricated with the ratio of water to cement of 0.4, 0.6, and 0.8. Secondly, the expansion of specimen immerged in sulphate solution is measured at different times. Thirdly, a theoretical model of expansion of cement mortar under sulphate erosion is suggested by virtue of represent volume element method. In this model, the damage evolution due to the interaction between delayed ettringite and cement mortar is taken into account. Finally, the numerical calculation is performed. The numerical and experimental results indicate that the model perfectly describes the expansion of the cement mortar.

Accurate GTO model for circuit simulations

The GTO model presented in this paper uses analytical expressions to describe the internal physics of the device. It has been implemented to run as compiled code in the SPICE simulation package and as a MAST template in the Saber simulator. A rigorous comparison of measured simulated waveforms and performance parameters (including turn-off energies) for a 3000A device is described and discussed.

Destruction-free parameter extraction for a physics-based circuit simulator IGCT model

This paper presents a practical destruction-free parameter extraction methodology for a new physics-based circuit simulator buffer-layer Integrated Gate Commutated Thyristor (IGCT) model. Most key parameters needed for this model can be extracted by one simple clamped inductive-load switching experiment. To validate this extraction method, a clamped inductive load switching experiment was performed, and corresponding simulations were carried out by employing the IGCT model with parameters extracted through the presented methodology. Good agreement has been obtained between the experimental data and simulation results.

Fourier spectrum based extraction of an equivalent trap state density in indium gallium zinc oxide transistors

Segregating the dynamics of gate bias induced threshold voltage shift, and in particular, charge trapping in thin film transistors (TFTs) based on time constants provides insight into the different mechanisms underlying TFTs instability. In this Letter we develop a representation of the time constants and model the magnitude of charge trapped in the form of an equivalent density of created trap states. This representation is extracted from the Fourier spectrum of the dynamics of charge trapping. Using amorphous In-Ga-Zn-O TFTs as an example, the charge trapping was modeled within an energy range of ΔEt 0.3 eV and with a density of state distribution as Dt(Et-j)=Dt0exp(-ΔEt/ kT)with Dt0 = 5.02 × 1011 cm-2 eV-1. Such a model is useful for developing simulation tools for circuit design. © 2014 AIP Publishing LLC.

A simulation model of body contact structure in PD SOI analogue circuit

As a solution of accurate simulation of the body effect in PD SOI analogue circuit, a simulation model of distributed body contact resistance and parasitical capacitance is presented. Based on this model, we have designed and simulated a sense amplifier that applied to V a 0.8um PD SOI 64K SRAM.

Circuit design and simulation of a CMOS-based preamplifier for brain neural signals

A novel CMOS-based preamplifier for amplifying brain neural signal obtained by scalp electrodes in brain-computer interface (BCI) is presented in this paper. By means of constructing effective equivalent input circuit structure of the preamplifier, two capacitors of 5 pF are included to realize the DC suppression compared to conventional preamplifiers. Then this preamplifier is designed and simulated using the standard 0.6 mu m MOS process technology model parameters with a supply voltage of 5 volts. With differential input structures adopted, simulation results of the preamplifier show that the input impedance amounts to more than 2 Gohm with brain neural signal frequency of 0.5 Hz-100 Hz. The equivalent input noise voltage is 18 nV/Hz(1/2). The common mode rejection ratio (CMRR) of 112 dB and the open-loop differential gain of 90 dB are achieved.