How to achieve high mobility thin film transistors by direct deposition of silicon using 13.56 MHz RF PECVD?

CMOS nanocrystalline silicon thin film transistors with high field effect mobility are reported. The transistors were directly deposited by radio-frequency plasma enhanced chemical vapor deposition at 150°C The transistors show maximum field effect mobility of 450 cm2/V-s for electrons and 100 cm2/V-s for holes at room temperature. We attribute the high mobilities to a reduction of the oxygen content, which acts as an accidental donor. Indeed, secondary ion mass spectrometry measurements show that the impurity concentration in the nanocrystalline Si layer is comparable to, or lower than, the defect density in the material, which is already low thanks to hydrogen passivation.

Fabrication of an organic field effect transistor using nano imprinting of Ag inks and semiconducting polymers

A simple and cheap procedure for flexible electronics fabrication was demonstrated by imprinting metallic nanoparticles (NPs) on flexible substrates. Silver NPs with an average diameter of 10 nm were prepared via an improved chemical approach and Ag Np ink was produced in α-terpineol with a concentration up to 15%. Silver micro/nanostructures with a dimension varying from nanometres to microns were produced on a flexible substrate (polyimide) by imprinting the as-prepared silver ink. The fine fluidic properties of an Ag NP/α-terpineol solution and low melting temperatures of silver nanoparticles render a low pressure and low temperature procedure, which is well suited for flexible electronics fabrication. The effects of sintering and mechanical bending on the conductivity of imprinted silver contacts were also investigated. Large area organic field effect transistors (OFET) on flexible substrates were fabricated using an imprinted silver electrode and semiconducting polymer. The OFET with silver electrodes imprinted from our prepared oleic acid stabilized Ag nanoparticle ink show an ideal ohmic contact; therefore, the OFET exhibit high performance (Ion/Ioff ratio: 1 × 103; mobility: 0.071 cm2 V-1 s-1). © 2010 IOP Publishing Ltd.

Dual gate photo-thin film transistor with high photoconductive gain for high reliability, and low noise flat panel transparent imager

In this presentation, we report excellent electrical and optical characteristics of a dual gate photo thin film transistor (TFT) with bi-layer oxide channel, which was designed to provide virgin threshold voltage (V T) control, improve the negative bias illumination temperature stress (NBITS) reliability, and offer high photoconductive gain. In order to address the photo-sensitivity of phototransistor for the incoming light, top transparent InZnO (IZO) gate was employed, which enables the independent gate control of dual gate photo-TFT without having any degradation of its photosensitivity. Considering optimum initial V T and NBITS reliability for the device operation, the top gate bias was judiciously chosen. In addition, the speed and noise performance of the photo-TFT is competitive with silicon photo-transistors, and more importantly, its superiority lies in optical transparency. © 2011 IEEE.

Temperature dependent electron transport in amorphous oxide semiconductor thin film transistors

A temperature-dependent mobility model in amorphous oxide semiconductor (AOS) thin film transistors (TFTs) extracted from measurements of source-drain terminal currents at different gate voltages and temperatures is presented. At low gate voltages, trap-limited conduction prevails for a broad range of temperatures, whereas variable range hopping becomes dominant at lower temperatures. At high gate voltages and for all temperatures, percolation conduction comes into the picture. In all cases, the temperature-dependent mobility model obeys a universal power law as a function of gate voltage. © 2011 IEEE.

200 v superjunction N-type lateral insulated-gate bipolar transistor with improved latch-up characteristics

This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong pnp transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (VON) of 2 V at 300 Acm2. The latch-up current density is 1100 Acm2. The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in VON. The latest design shows a latch-up current density of 1195 A cm2. The enhanced robustness against static latch-up leads to a better forward bias safe operating area. © 1963-2012 IEEE.

Analysis of amorphous indium-gallium-zinc-oxide thin-film transistor contact metal using Pilling-Bedworth theory and a variable capacitance diode model

It is widely reported that threshold voltage and on-state current of amorphous indium-gallium-zinc-oxide bottom-gate thin-film transistors are strongly influenced by the choice of source/drain contact metal. Electrical characterisation of thin-film transistors indicates that the electrical properties depend on the type and thickness of the metal(s) used. Electron transport mechanisms and possibilities for control of the defect state density are discussed. Pilling-Bedworth theory for metal oxidation explains the interaction between contact metal and amorphous indium-gallium-zinc-oxide, which leads to significant trap formation. Charge trapping within these states leads to variable capacitance diode-like behavior and is shown to explain the thin-film transistor operation. © 2013 AIP Publishing LLC.

Non-ohmic contact resistance and field-effect mobility in nanocrystalline silicon thin film transistors

Contact resistance has a significant impact on the electrical characteristics of thin film transistors. It limits their maximum on-current and affects their subsequent behavior with bias. This distorts the extracted device parameters, in particular, the field-effect mobility. This letter presents a method capable of accounting for both the non-ohmic (nonlinear) and ohmic (linear) contact resistance effects solely based upon terminal I-V measurements. Applying our analysis to a nanocrystalline silicon thin film transistor, we demonstrate that contact resistance effects can lead to a twofold underestimation of the field-effect mobility. © 2008 American Institute of Physics.

Electrical detection of trapped charge displacements using an ultra-thin SOI percolation transistor

Electrical detection of solid-state charge qubits requires ultrasensitive charge measurement, typically using a quantum point contact or single-electron-transistor, which imposes strict limits on operating temperature, voltage and current. A conventional FET offers relaxed operating conditions, but the back-action of the channel charge is a problem for such small quantum systems. Here, we discuss the use of a percolation transistor as a measurement device, with regard to charge sensing and backaction. The transistor is based on a 10nm thick SOI channel layer and is designed to measure the displacement of trapped charges in a nearby dielectric. At cryogenic temperatures, the trapped charges result in strong disorder in the channel layer, so that current is constrained to a percolation pathway in sub-threshold conditions. A microwave driven spatial Rabi oscillation of the trapped charge causes a change in the percolation pathway, which results in a measurable change in channel current. © The Electrochemical Society.

High-performance nanowire oxide photo-thin film transistor.

A gate-modulated nanowire oxide photosensor is fabricated by electron-beam lithography and conventional dry etch processing.. The device characteristics are good, including endurance of up to 10(6) test cycles, and gate-pulse excitation is used to remove persistent photoconductivity. The viability of nanowire oxide phototransistors for high speed and high resolution applications is demonstrated, thus potentially expanding the scope of exploitation of touch-free interactive displays.

Gigahertz multi-transistor graphene integrated circuits

We review the potential of graphene in ultra-high speed circuits. To date, most of high-frequency graphene circuits typically consist of a single transistor integrated with a few passive components. The development of multi-transistor graphene integrated circuits operating at GHz frequencies can pave the way for applications in which high operating speed is traded off against power consumption and circuit complexity. Novel vertical and planar devices based on a combination of graphene and layered materials could broaden the scope and performances of future devices. © 2013 IEEE.

Neutron irradiation effect in two-dimensional electron gas of AlGaN/GaN heterostructures

AlGaN/GaN heterostructures have been irradiated by neutrons with different influences and characterized by means of temperature-dependent Hall measurements and Micro-Raman scattering techniques. It is found that the carrier mobility of two-dimensional electron gas (2DEG) is very sensitive to neutrons. At a low influence of 6.13 x 10(15) cm(-2), the carrier mobility drops sharply, while the sheet carrier density remains the same as that of an unirradiated sample. Moreover, even for a fluence of up to 3.66 x 10(16) cm(-2), the sheet carrier density shows only a slight drop. We attribute the degradation of the figure-of-merit (product of n(s) x mu) of 2DEG to the defects induced by neutron irradiation. Raman measurements show that neutron irradiation does not yield obvious change to the strain state of AlGaN/GaN heterostructures, which proves that degradation of sheet carrier density has no relation to strain relaxation in the present study. The increase of the product of n(s) x mu of 2DEG during rapid thermal annealing processes at relatively high temperature has been attributed to the activation of Ge-Ga transmuted from Ga and the recovery of displaced defects.

Quantum mechanical simulation of nanosized metal-oxide-semiconductor field-effect transistor using empirical pseudopotentials: A comparison for charge density occupation methods

The atomistic pseudopotential quantum mechanical calculations are used to study the transport in million atom nanosized metal-oxide-semiconductor field-effect transistors. In the charge self-consistent calculation, the quantum mechanical eigenstates of closed systems instead of scattering states of open systems are calculated. The question of how to use these eigenstates to simulate a nonequilibrium system, and how to calculate the electric currents, is addressed. Two methods to occupy the electron eigenstates to yield the charge density in a nonequilibrium condition are tested and compared. One is a partition method and another is a quasi-Fermi level method. Two methods are also used to evaluate the current: one uses the ballistic and tunneling current approximation, another uses the drift-diffusion method. (C) 2009 American Institute of Physics. [doi:10.1063/1.3248262]