Do healthy cities work? A logic of method for assessing impact and outcome of healthy cities

In this article, we discuss an appropriate methodology for assessing complex urban programs such as the WHO European Healthy Cities Network. The basic tenets and parameters for this project are reviewed, and situated in the broader urban health tradition. This leads to a delineation of the types of questions researchers can address when looking at a complex urban health program. Such questions reach appropriately beyond traditional public health concepts involving proximal and distal determinants of health (and associated upstream, midstream, and downstream rhetoric). Espousing a multi-level, reciprocal pathways perspective on Healthy Cities research, we also adopt a distinction between impacts and outcomes of Healthy Cities. The former are value driven, the latter intervention-driven. These approaches lead to the acknowledgment of a logic of method that includes situational and contextual appreciation of unique Healthy City experiences in a Realist Evaluation paradigm. The article concludes with a reflection of evaluation and assessment procedures applied to Phase IV (2003-2008) of the WHO European Healthy Cities Network and an interpretation of response rates to the range of methods that have been adopted.

Intelligent 3D programmable surface

Creating a highly programmable surface operating at relatively high speed and in real time is an area of research with many challenges. Such a system has applications in the field of optical telescopes, product manufacturing, and giant 3D-screens and billboards for advertising and artwork. This paper covers certain aspects of a keynote presentation at ISDT 2010 including system design, modularity, programmability and the system control intelligence. An overview of the system architecture, actuator design, electronics and distributed control will provide an insight into how the system is controlled and self-tuned for a number of applications. A simulation environment that has been developed to streamline system reconfiguration will also be presented, demonstrating translation of complex mathematical functions into 3D shapes virtually before being displayed on the physical surface.

A head mountable deep brain stimulation device for laboratory animals

Deep brain stimulation has emerged as an effective method to treat certain medical conditions. Electrical charges are injected into the target tissue through a conducting electrode exciting the tissue. A variety of DBS devices have been developed based on different operation principles. Majority of these devices, however, employ complex circuitry and are bulky. In clinical trials, laboratory animals need to freely move around and perform activities whilst receiving brain stimulation for days. This paper presents a simple lightweight head mountable deep brain stimulation device that can be carried by the animal during the course of a clinical trial. The device produces continuous current pulses of specific characteristics. It employs passive charge balancing to minimize undesirable effects on the target tissue. The device is constructed and its performance tested.

Anaesthesia monitoring using fuzzy logic

Objective. Humans have a limited ability to accurately and continuously analyse large amount of data. In recent times, there has been a rapid growth in patient monitoring and medical data analysis using smart monitoring systems. Fuzzy logic-based expert systems, which can mimic human thought processes in complex circumstances, have indicated potential to improve clinicians' performance and accurately execute repetitive tasks to which humans are ill-suited. The main goal of this study is to develop a clinically useful diagnostic alarm system based on fuzzy logic for detecting critical events during anaesthesia administration. Method. The proposed diagnostic alarm system called fuzzy logic monitoring system (FLMS) is presented. New diagnostic rules and membership functions (MFs) are developed. In addition, fuzzy inference system (FIS), adaptive neuro fuzzy inference system (ANFIS), and clustering techniques are explored for developing the FLMS' diagnostic modules. The performance of FLMS which is based on fuzzy logic expert diagnostic systems is validated through a series of offline tests. The training and testing data set are selected randomly from 30 sets of patients' data. Results. The accuracy of diagnoses generated by the FLMS was validated by comparing the diagnostic information with the one provided by an anaesthetist for each patient. Kappa-analysis was used for measuring the level of agreement between the anaesthetist's and FLMS's diagnoses. When detecting hypovolaemia, a substantial level of agreement was observed between FLMS and the human expert (the anaesthetist) during surgical procedures. Conclusion. The diagnostic alarm system FLMS demonstrated that evidence-based expert diagnostic systems can diagnose hypovolaemia, with a substantial degree of accuracy, in anaesthetized patients and could be useful in delivering decision support to anaesthetists.

A low power micro deep brain stimulation device for murine preclinical research

Deep brain stimulation has emerged as an effective medical procedure that has therapeutic efficacy in a number of neuropsychiatric disorders. Preclinical research involving laboratory animals is being conducted to study the principles, mechanisms, and therapeutic effects of deep brain stimulation. A bottleneck is, however, the lack of deep brain stimulation devices that enable long term brain stimulation in freely moving laboratory animals. Most of the existing devices employ complex circuitry, and are thus bulky. These devices are usually connected to the electrode that is implanted into the animal brain using long fixed wires. In long term behavioral trials, however, laboratory animals often need to continuously receive brain stimulation for days without interruption, which is difficult with existing technology. This paper presents a low power and lightweight portable microdeep brain stimulation device for laboratory animals. Three different configurations of the device are presented as follows: 1) single piece head mountable; 2) single piece back mountable; and 3) two piece back mountable. The device can be easily carried by the animal during the course of a clinical trial, and that it can produce non-stop stimulation current pulses of desired characteristics for over 12 days on a single battery. It employs passive charge balancing to minimize undesirable effects on the target tissue. The results of bench, in-vitro, and in-vivo tests to evaluate the performance of the device are presented.

Control of polystyrene batch reactor using fuzzy logic controller

Control of polymerization reactors is a challenging issue for researchers due to the complex reaction mechanisms. A lot of reactions occur simultaneously during polymerization. This leads to a polymerization system that is highly nonlinear in nature. In this work, a nonlinear advanced controller, named fuzzy logic controller (FLC), is developed for monitoring the batch free radical polymerization of polystyrene (PS) reactor. Temperature is used as an intermediate control variable to control polymer quality, because the products quality and quantity of polymer are directly depends on temperature. Different FLCs are developed through changing the number of fuzzy membership functions (MFs) for inputs and output. The final tuned FLC results are compared with the results of another advanced controller, named neural network based model predictive controller (NN-MPC). The simulation results reveal that the FLC performance is better than NN-MPC in terms of quantitative and qualitative performance criterion.

A highly interactive 3D programmable surface

Abstract : This presentation will focus on design, modularity, development and control of a highly interactive programmable surface created within the CISR. The system is comprised of thousands of pneumatic cylinders controlled simultaneously in real-time to create a highly dynamic and responsive 3 dimensional surface. The idea behind this research project was the creation of a dynamically responsive surface that configures in real-time according to input from a variety of electronic inputs (movements, sound, etc). The surface is also viewed potentially as a universal motional simulator platform. A simulator that was developed for ease of system reconfiguration demonstrates the translation of complex mathematical functions into 3D shapes in the virtual world before being generated on the real surface. Application areas span from optical telescope to product manufacturing and giant 3D screens billboards for advertising and artwork.

Contribuição para o estudo do embarque de uma rede neural artificial em field programmable gate array (FPGA)

This study shows the implementation and the embedding of an Artificial Neural Network (ANN) in hardware, or in a programmable device, as a field programmable gate array (FPGA). This work allowed the exploration of different implementations, described in VHDL, of multilayer perceptrons ANN. Due to the parallelism inherent to ANNs, there are disadvantages in software implementations due to the sequential nature of the Von Neumann architectures. As an alternative to this problem, there is a hardware implementation that allows to exploit all the parallelism implicit in this model. Currently, there is an increase in use of FPGAs as a platform to implement neural networks in hardware, exploiting the high processing power, low cost, ease of programming and ability to reconfigure the circuit, allowing the network to adapt to different applications. Given this context, the aim is to develop arrays of neural networks in hardware, a flexible architecture, in which it is possible to add or remove neurons, and mainly, modify the network topology, in order to enable a modular network of fixed-point arithmetic in a FPGA. Five synthesis of VHDL descriptions were produced: two for the neuron with one or two entrances, and three different architectures of ANN. The descriptions of the used architectures became very modular, easily allowing the increase or decrease of the number of neurons. As a result, some complete neural networks were implemented in FPGA, in fixed-point arithmetic, with a high-capacity parallel processing

A 2kW interleaved ZCS-FM boost rectifier digitally controlled by FPGA device

This paper presents a 2kW single-phase high power factor boost rectifier with four cells in interleave connection, operating in critical conduction mode, and employing a soft-switching technique, controlled by Field Programmable Gate Array (FPGA). The soft-switching technique Is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-voltage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related 'to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the Interleaving technique, the rectifer's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) In the input current, in compliance with the TEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for four interleaved cells, and a closed-loop to provide the output voltage regulation, like as a pre-regulator rectifier. Experimental results are presented for a 2kW implemented prototype with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.

On designing OTA-C graphic-equalizers with MOSFET-triode transconductors

A CMOS audio-equalizer based on a parallel-array of 2nd-order bandpass-sections is presented and realized with triode transconductors. It has a programmable 12db-boost/cut on each of its three decade-bands, easily achieved through the linear dependence of gm on VDS. In accordance with a 0.8μm n-well double-metal fabrication process, a range of simulations supports theoretical analysis and circuit performance at different boost/cut scenarios. For VDD=3.3V, fullboosting stand-by prover consumption is 1.05mW. THD=-42.61dB@1Vpp and may be improved by balanced structures. Thermal- and I/f-noise spectral densities are 3.2μV/Hz12 and 18.2μV/Hz12@20Hz, respectively, for a dynamic range of 52.3dB@1Vpp. The equalizer effective area is 2.4mm2. The drawback of the existing transmission-zero due to the feedthrough-capacitance of a triode input-device is also addressed. The proposed topology can be extended to the design of more complex graphic-equalizers and hearing-aids.

A low-voltage programmable-gain CMOS amplifier with very-low temperature-drift

A new topology for a LVLP variable-gain CMOS amplifier is presented. Input- and load-stage are built around triode-transconductors so that voltage-gain is fully defined by a linear relationship involving only device-geometries and biases. Excellent gain-accuracy, temperature-insensitivity; and wide range of programmability, are thus achieved. Moreover, adaptative biasing improves the common-mode voltage stability upon gain-adjusting. As an example, a 0-40dB programmablegain audio-amplifier is designed. Its performance is supported by a range of simulations. For VDD=1.8V and 20dB-nominal gain, one has Av=19.97dB, f3db=770KHz and quiescent dissipation of 378μW. Over temperatures from -25°C to 125°C, the 0. ldB-bandwidth is 52KHz. Dynamic-range is optimized to 57.2dB and 42.6dB for gains of 20dB and 40dB, respectively. THD figures correspond to -60.6dB@Vout= 1Vpp and -79.7dB@Vout= 0.5 Vpp. A nearly constant bandwidth for different gains is also attained.

An AC voltage regulator with high-power-factor, and control using a FPGA device

This paper presents the analysis, design, simulation, and experimental results for a high frequency high Power-Factor (PF) AC (Alternate Current) voltage regulator, using a Sepic converter as power stage. The control technique employed to impose a sinusoidal input current waveform, with low Total Harmonic Distortion (THD), is the sinusoidal variable hysteresis control. The control technique was implemented in a FPGA (Field Programmable Gate Array) device, using a Hardware Description Language (VHDL). Through the use of the proposed control technique, the AC voltage regulator performs active power-factor correction, and low THD in the input current, for linear and non-linear loads, satisfying the requirements of the EEC61000-3-2 standards. Experimental results from an example prototype, designed for 300W of nominal output power, 50kHz (switching frequency), and 127Vrms of nominal input and output voltages, are presented in order to validate the proposed AC regulator. © 2005 IEEE.

A true programmable HPF hybrid three-phase rectifier

In this paper is proposed and analyzed a digital hysteresis modulation using a FPGA (Field Programmable Gate Array) device and VHDL (Hardware Description Language), applied at a hybrid three-phase rectifier with almost unitary input power factor, composed by parallel SEPIC controlled single-phase rectifiers connected to each leg of a standard 6-pulses uncontrolled diode rectifier. The digital control allows a programmable THD (Total Harmonic Distortion) at the input currents, and it makes possible that the power rating of the switching-mode converters, connected in parallel, can be a small fraction of the total average output power, in order to obtain a compact converter, reduced input current THD and almost unitary input power factor. The proposed digital control, using a FPGA device and VHDL, offers an important flexibility for the associated control technique, in order to obtain a programmable PFC (Power Factor Correction) hybrid three-phase rectifier, in agreement with the international standards (IEC, and IEEE), which impose limits for the THD of the AC (Alternate Current) line input currents. Finally, the proposed control strategy is verified through experimental results from an implemented prototype. ©2008 IEEE.

Fatigue apparatus for geometrically complex non-standardized specimens

Standard Test Methods (e.g. ASTM, DIN) for materials characterization in general, and for fatigue in particular, do not contemplate specimens with complex geometries, as well as the combination of axial and in-plane bending loads in their methodologies. The present study refers to some patents and the new configuration or configurations of specimens (non-standardized by the status quo of test methods) and a device developed to induce axial and bending combined forces resultants from axial loads applied by any one test equipment (dynamic or monotonic) which possesses such limitation, towards obtaining more realistic results on the fatigue behavior, or even basic mechanical properties, from geometrically complex structures. Motivated by a specific and geometrically complex aeronautic structure (motor-cradle), non-standardized welded tubular specimens made from AISI 4130 steel were fatigue-tested at room temperature, by using a constant amplitude sinusoidal load of 20 Hz frequency, load ratio R = 0.1 with and without the above referred auxiliary fatigue apparatus. The results showed the fatigue apparatus was efficient for introducing higher stress concentration factor at the welded specimen joints, consequently reducing the fatigue strength when compared to other conditions. From the obtained results it is possible to infer that with small modifications the proposed apparatus will be capable to test a great variety of specimen configurations such as: squared tubes and plates with welded or melted junctions, as well as other materials such as aluminum, titanium, composites, polymeric, plastics, etc. © 2009 Bentham Science Publishers Ltd.

Hardware implementation of type-2 programmable fuzzifier

The design of full programmable type-2 membership function circuit is presented in this paper. This circuit is used to implement the fuzzifier block of Type-2 Fuzzy Logic Controller chip. In this paper the type-2 fuzzy set was obtained by blurring the width of the type-1 fuzzy set. This circuit allows programming the height and the shape of the membership function. It operates in current mode, with supply voltage of 3.3V. The simulation results of interval type-2 membership function circuit have been done in CMOS 0.35μm technology using Mentor Graphics software. © 2011 IEEE.