Effect of X-ray tube parameters, iodine concentration, and patient size on image quality in pulmonary computed tomography angiography: a chest-phantom-study

OBJECTIVES: The aim of this phantom study was to evaluate the contrast-to-noise ratio (CNR) in pulmonary computed tomography (CT)-angiography for 300 and 400 mg iodine/mL contrast media using variable x-ray tube parameters and patient sizes. We also analyzed the possible strategies of dose reduction in patients with different sizes. MATERIALS AND METHODS: The segmental pulmonary arteries were simulated by plastic tubes filled with 1:30 diluted solutions of 300 and 400 mg iodine/mL contrast media in a chest phantom mimicking thick, intermediate, and thin patients. Volume scanning was done with a CT scanner at 80, 100, 120, and 140 kVp. Tube current-time products (mAs) varied between 50 and 120% of the optimal value given by the built-in automatic dose optimization protocol. Attenuation values and CNR for both contrast media were evaluated and compared with the volume CT dose index (CTDI(vol)). Figure of merit, calculated as CNR/CTDIvol, was used to quantify image quality improvement per exposure risk to the patient. RESULTS: Attenuation of iodinated contrast media increased both with decreasing tube voltage and patient size. A CTDIvol reduction by 44% was achieved in the thin phantom with the use of 80 instead of 140 kVp without deterioration of CNR. Figure of merit correlated with kVp in the thin phantom (r = -0.897 to -0.999; P < 0.05) but not in the intermediate and thick phantoms (P = 0.09-0.71), reflecting a decreasing benefit of tube voltage reduction on image quality as the thickness of the phantom increased. Compared with the 300 mg iodine/mL concentration, the same CNR for 400 mg iodine/mL contrast medium was achieved at a lower CTDIvol by 18 to 40%, depending on phantom size and applied tube voltage. CONCLUSIONS: Low kVp protocols for pulmonary embolism are potentially advantageous especially in thin and, to a lesser extent, in intermediate patients. Thin patients profit from low voltage protocols preserving a good CNR at a lower exposure. The use of 80 kVp in obese patients may be problematic because of the limitation of the tube current available, reduced CNR, and high skin dose. The high CNR of the 400 mg iodine/mL contrast medium together with lower tube energy and/or current can be used for exposure reduction.

EVALUATION OF MAGNESIUM AS A HALL THRUSTER PROPELLANT

In this study, the use of magnesium as a Hall thruster propellant was evaluated. A xenon Hall thruster was modified such that magnesium propellant could be loaded into the anode and use waste heat from the thruster discharge to drive the propellant vaporization. A control scheme was developed, which allowed for precise control of the mass flow rate while still using plasma heating as the main mechanism for evaporation. The thruster anode, which also served as the propellant reservoir, was designed such that the open area was too low for sufficient vapor flow at normal operating temperatures (i.e. plasma heating alone). The remaining heat needed to achieve enough vapor flow to sustain thruster discharge came from a counter-wound resistive heater located behind the anode. The control system has the ability to arrest thermal runaway in a direct evaporation feed system and stabilize the discharge current during voltage-limited operation. A proportional-integral-derivative control algorithm was implemented to enable automated operation of the mass flow control system using the discharge current as the measured variable and the anode heater current as the controlled parameter. Steady-state operation at constant voltage with discharge current excursions less than 0.35 A was demonstrated for 70 min. Using this long-duration method, stable operation was achieved with heater powers as low as 6% of the total discharge power. Using the thermal mass flow control system the thruster operated stably enough and long enough that performance measurements could be obtained and compared to the performance of the thruster using xenon propellant. It was found that when operated with magnesium, the thruster has thrust ranging from 34 mN at 200 V to 39 mN at 300 V with 1.7 mg/s of propellant. It was found to have 27 mN of thrust at 300 V using 1.0 mg/s of propellant. The thrust-to-power ratio ranged from 24 mN/kW at 200 V to 18 mN/kW at 300 volts. The specific impulse was 2000 s at 200 V and upwards of 2700 s at 300 V. The anode efficiency was found to be ~23% using magnesium, which is substantially lower than the 40% anode efficiency of xenon at approximately equivalent molar flow rates. Measurements in the plasma plume of the thruster—operated using magnesium and xenon propellants—were obtained using a Faraday probe to measure off-axis current distribution, a retarding potential analyzer to measure ion energy, and a double Langmuir probe to measure plasma density, electron temperature, and plasma potential. Additionally, the off axis current distributions and ion energy distributions were compared to measurements made in krypton and bismuth plasmas obtained in previous studies of the same thruster. Comparisons showed that magnesium had the largest beam divergence of the four propellants while the others had similar divergence. The comparisons also showed that magnesium and krypton both had very low voltage utilization compared to xenon and bismuth. It is likely that the differences in plume structure are due to the atomic differences between the propellants; the ionization mean free path goes down with increasing atomic mass. Magnesium and krypton have long ionization mean free paths and therefore require physically larger thruster dimensions for efficient thruster operation and would benefit from magnetic shielding.

Regional myocardial wall thinning at multidetector computed tomography correlates to arrhythmogenic substrate in postinfarction ventricular tachycardia: assessment of structural and electrical substrate

BACKGROUND A majority of patients undergoing ablation of ventricular tachycardia have implanted devices precluding substrate imaging with delayed-enhancement MRI. Contrast-enhanced multidetector computed tomography (MDCT) can depict myocardial wall thickness with submillimetric resolution. We evaluated the relationship between regional myocardial wall thinning (WT) imaged by MDCT and arrhythmogenic substrate in postinfarction ventricular tachycardia. METHODS AND RESULTS We studied 13 consecutive postinfarction patients undergoing MDCT before ablation. MDCT data were integrated with high-density 3-dimensional electroanatomic maps acquired during sinus rhythm (endocardium, 509±291 points/map; epicardium, 716±323 points/map). Low-voltage areas (<1.5 mV) and local abnormal ventricular activities (LAVA) during sinus rhythm were assessed with regard to the WT. A significant correlation was found between the areas of WT <5 mm and endocardial low voltage (correlation-R=0.82; P=0.001), but no such correlation was found in the epicardium. The WT <5 mm area was smaller than the endocardial low-voltage area (54 cm(2) [Q1-Q3, 46-92] versus 71 cm(2) [Q1-Q3, 59-124]; P=0.001). Among a total of 13 060 electrograms reviewed in the whole study population, 538 LAVA were detected and analyzed. LAVA were located within the WT <5 mm (469/538 [87%]) or at its border (100% within 23 mm). Very late LAVA (>100 ms after QRS complex) were almost exclusively detected within the thinnest area (93% in the WT<3 mm). CONCLUSIONS Regional myocardial WT correlates to low-voltage regions and distribution of LAVA critical for the generation and maintenance of postinfarction ventricular tachycardia. The integration of MDCT WT with 3-dimensional electroanatomic maps can help focus mapping and ablation on the culprit regions, even when MRI is precluded by the presence of implanted devices.

Integration of merged delayed-enhanced magnetic resonance imaging and multidetector computed tomography for the guidance of ventricular tachycardia ablation: a pilot study

BACKGROUND Delayed enhancement (DE) MRI can assess the fibrotic substrate of scar-related VT. MDCT has the advantage of inframillimetric spatial resolution and better 3D reconstructions. We sought to evaluate the feasibility and usefulness of integrating merged MDCT/MRI data in 3D-mapping systems for structure-function assessment and multimodal guidance of VT mapping and ablation. METHODS Nine patients, including 3 ischemic cardiomyopathy (ICM), 3 nonischemic cardiomyopathy (NICM), 2 myocarditis, and 1 redo procedure for idiopathic VT, underwent MRI and MDCT before VT ablation. Merged MRI/MDCT data were integrated in 3D-mapping systems and registered to high-density endocardial and epicardial maps. Low-voltage areas (<1.5 mV) and local abnormal ventricular activities (LAVA) during sinus rhythm were correlated to DE at MRI, and wall-thinning (WT) at MDCT. RESULTS Endocardium and epicardium were mapped with 391 ± 388 and 1098 ± 734 points per map, respectively. Registration of MDCT allowed visualization of coronary arteries during epicardial mapping/ablation. In the idiopathic patient, integration of MRI data identified previously ablated regions. In ICM patients, both DE at MRI and WT at MDCT matched areas of low voltage (overlap 94 ± 6% and 79 ± 5%, respectively). In NICM patients, wall-thinning areas matched areas of low voltage (overlap 63 ± 21%). In patients with myocarditis, subepicardial DE matched areas of epicardial low voltage (overlap 92 ± 12%). A total number of 266 LAVA sites were found in 7/9 patients. All LAVA sites were associated to structural substrate at imaging (90% inside, 100% within 18 mm). CONCLUSION The integration of merged MDCT and DEMRI data is feasible and allows combining substrate assessment with high-spatial resolution to better define structure-function relationship in scar-related VT.

Measuring the bending of asymmetric planar EAP structures

The geometric characterization of low-voltage dielectric electro-active polymer (EAP) structures, comprised of nanometer thickness but areas of square centimeters, for applications such as artificial sphincters requires methods with nanometer precision. Direct optical detection is usually restricted to sub-micrometer resolution because of the wavelength of the light applied. Therefore, we propose to take advantage of the cantilever bending system with optical readout revealing a sub-micrometer resolution at the deflection of the free end. It is demonstrated that this approach allows us to detect bending of rather conventional planar asymmetric, dielectric EAP-structures applying voltages well below 10 V. For this purpose, we built 100 μm-thin silicone films between 50 nm-thin silver layers on a 25 μm-thin polyetheretherketone (PEEK) substrate. The increase of the applied voltage in steps of 50 V until 1 kV resulted in a cantilever bending that exhibits only in restricted ranges the expected square dependence. The mean laser beam displacement on the detector corresponded to 6 nm per volt. The apparatus will therefore become a powerful mean to analyze and thereby improve low-voltage dielectric EAP-structures to realize nanometer-thin layers for stack actuators to be incorporated into artificial sphincter systems for treating severe urinary and fecal incontinence.

Optimal dose levels in screening chest CT for unimpaired detection and volumetry of lung nodules, with and without computer assisted detection at minimal patient radiation

OBJECTIVES The aim of this phantom study was to minimize the radiation dose by finding the best combination of low tube current and low voltage that would result in accurate volume measurements when compared to standard CT imaging without significantly decreasing the sensitivity of detecting lung nodules both with and without the assistance of CAD. METHODS An anthropomorphic chest phantom containing artificial solid and ground glass nodules (GGNs, 5-12 mm) was examined with a 64-row multi-detector CT scanner with three tube currents of 100, 50 and 25 mAs in combination with three tube voltages of 120, 100 and 80 kVp. This resulted in eight different protocols that were then compared to standard CT sensitivity (100 mAs/120 kVp). For each protocol, at least 127 different nodules were scanned in 21-25 phantoms. The nodules were analyzed in two separate sessions by three independent, blinded radiologists and computer-aided detection (CAD) software. RESULTS The mean sensitivity of the radiologists for identifying solid lung nodules on a standard CT was 89.7% ± 4.9%. The sensitivity was not significantly impaired when the tube and current voltage were lowered at the same time, except at the lowest exposure level of 25 mAs/80 kVp [80.6% ± 4.3% (p = 0.031)]. Compared to the standard CT, the sensitivity for detecting GGNs was significantly lower at all dose levels when the voltage was 80 kVp; this result was independent of the tube current. The CAD significantly increased the radiologists' sensitivity for detecting solid nodules at all dose levels (5-11%). No significant volume measurement errors (VMEs) were documented for the radiologists or the CAD software at any dose level. CONCLUSIONS Our results suggest a CT protocol with 25 mAs and 100 kVp is optimal for detecting solid and ground glass nodules in lung cancer screening. The use of CAD software is highly recommended at all dose levels.

The diagnostic value of a 12-lead electrocardiogram in patients with cardiac tamponade due to a malignant pericardial effusion

Background. Cardiac tamponade can occur when a large amount of fluid, gas, singly or in combination, accumulating within the pericardium, compresses the heart causing circulatory compromise. Although previous investigators have found the 12-lead ECG to have a poor predictive value in diagnosing cardiac tamponade, very few studies have evaluated it as a follow up tool for ruling in or ruling out tamponade in patients with previously diagnosed malignant pericardial effusions. ^ Methods. 127 patients with malignant pericardial effusions at the MD Anderson Cancer Center were included in this retrospective study. While 83 of these patients had a cardiac tamponade diagnosed by echocardiographic criteria (Gold standard), 44 did not. We computed the sensitivity (Se), specificity (Sp), positive (PPV) and negative predictive values (NPV) for individual and combinations of ECG abnormalities. Individual ECG abnormalities were also entered singly into a univariate logistic regression model to predict tamponade. ^ Results. For patients with effusions of all sizes, electrical alternans had a Se, Sp, PPV and NPV of 22.61%, 97.61%, 95% and 39.25% respectively. These parameters for low voltage complexes were 55.95%, 74.44%, 81.03%, 46.37% respectively. The presence of all three ECG abnormalities had a Se = 8.33%, Sp = 100%, PPV = 100% and NPV = 35.83% while the presence of at least one of the three ECG abnormalities had a Se = 89.28%, Sp = 46.51%, PPV = 76.53%, NPV = 68.96%. For patients with effusions of all sizes electrical alternans had an OR of 12.28 (1.58–95.17, p = 0.016), while the presence of at least one ECG abnormality had an OR of 7.25 (2.9–18.1, p = 0.000) in predicting tamponade. ^ Conclusions. Although individual ECG abnormalities had low sensitivities, specificities, NPVs and PPVs with the exception of electrical alternans, the presence of at least one of the three ECG abnormalities had a high sensitivity in diagnosing cardiac tamponade. This could point to its potential use as a screening test with a correspondingly high NPV to rule out a diagnosis of tamponade in patients with malignant pericardial effusions. This could save expensive echocardiographic assessments in patients with previously diagnosed pericardial effusions. ^

Table 2 Analytical data of the samples by the "Dipole CHIM" at the Yingezhuang gold deposit

CHIM method involves extracting metal ions of electromobile forms in either anodes or cathodes, facilitated by a man-made electric field. This paper presents two newly developed CHIM alternatives that are electrified by a low voltage dipole. The firstly improved technique enables cationic ions to be extracted in a single cathode, whereas the secondly improved technique allows both anionic and cationic species to be extracted simultaneously in an anode and in a cathode. Compared with the traditional CHIM methods, the innovative techniques developed in this paper are characterized by simple instrumentation, low cost and easy operation in field, and in particular enables simultaneous extraction of anionic and cationic species of elements, from which more information can be derived with higher extraction efficiency. Field tests at several well-known mine areas in China confirm the effectiveness and efficiency of the new techniques in exploring for deeply buried ore bodies.

Experience with PV-diesel hybrid village power systems in southern Morocco

In October 2002, under the auspices of Spanish Cooperation, a pilot electrification project put into operation two centralised PV-diesel hybrid systems in two different Moroccan villages. These systems currently provide a full-time energy service and supply electricity to more than a hundred of families, six community buildings, street lighting and one running water system. The appearance of the electricity service is very similar to an urban one: one phase AC supply (230V/50Hz) distributed up to each dwelling using a low-voltage mini-grid, which has been designed to be fully compatible with a future arrival of the utility grid. The management of this electricity service is based on a “fee-for-service” scheme agreed between a local NGO, partner of the project, and electricity associations created in each village, which are in charge of, among other tasks, recording the daily energy production of systems and the monthly energy consumption of each house. This register of data allows a systematic evaluation of both the system performance and the energy consumption of users. Now, after four years of operation, this paper presents the experience of this pilot electrification project and draws lessons that can be useful for designing, managing and sizing this type of small village PV-hybrid system

Use of STATCOM in wind farms with fixed-speed generators for grid code compliance

The increasing penetration of wind energy into power systems has pushed grid operators to set new requirements for this kind of generating plants in order to keep acceptable and reliable operation of the system. In addition to the low voltage ride through capability, wind farms are required to participate in voltage support, stability enhancement and power quality improvement. This paper presents a solution for wind farms with fixed-speed generators based on the use of STATCOM with braking resistor and additional series impedances, with an adequate control strategy. The focus is put on guaranteeing the grid code compliance when the wind farm faces an extensive series of grid disturbances.

2D tunable graded index prism beam steering device based on nematic liquid crystals

Liquid crystal devices are being used in many non-display applications in order to construct small devices controlled by low voltage electronics without mechanical components. In this work, we present a novel liquid crystal device for laser beam steering. In this device the orientation of the liquid crystal molecules can be controlled. A change in the liquid crystal orientation results in a change of the refractive index. When a laser beam passes through the device, the beam will be deviated (Fig.1) and the device works a prism. The main difference between this device and a prism is that in the device the orientation profile of the liquid crystal molecules can be modified so that the laser beam can be deviated a required angle: the device is tuneable.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en técnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en inglés), que han sido propuestas dentro del campo de investigación académica desde hace 17 años. Las investigaciones relacionadas han experimentado un notable crecimiento en las últimas décadas, mientras que los diseños enfocados en la protección sólida y eficaz contra dichos ataques aún se mantienen como un tema de investigación abierto, en el que se necesitan iniciativas más confiables para la protección de la información persona de empresa y de datos nacionales. El primer uso documentado de codificación secreta se remonta a alrededor de 1700 B.C., cuando los jeroglíficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la información siempre ha supuesto un factor clave en la transmisión de datos relacionados con inteligencia diplomática o militar. Debido a la evolución rápida de las técnicas modernas de comunicación, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisión a través de cables sin seguridad o medios inalámbricos. Debido a las restricciones de potencia de cálculo antes de la era del ordenador, la técnica de cifrado simple era un método más que suficiente para ocultar la información. Sin embargo, algunas vulnerabilidades algorítmicas pueden ser explotadas para restaurar la regla de codificación sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el área de la criptografía, con el fin de proteger el sistema de información ante sofisticados algoritmos. Con la invención de los ordenadores se ha acelerado en gran medida la implementación de criptografía segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computación altamente reforzadas. Igualmente, sofisticados cripto-análisis han impulsado las tecnologías de computación. Hoy en día, el mundo de la información ha estado involucrado con el campo de la criptografía, enfocada a proteger cualquier campo a través de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificación optimizada de teorías matemáticas modernas y prácticas eficaces de hardware, siendo posible su implementación en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales métricas de conducción en el diseño electrónico, con el objetivo de promover la fabricación de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementación práctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de análisis. Sin embargo, algunas críticas sobre los algoritmos criptográficos teóricamente seguros surgieron casi inmediatamente después de este descubrimiento. En este sentido, los circuitos digitales consisten típicamente en un gran número de celdas lógicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricación. La lógica de los circuitos se realiza en función de las innumerables conmutaciones de estas células. Este mecanismo provoca inevitablemente cierta emanación física especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptografía de claves), analizar la arquitectura lógica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparación de correlación entre la cantidad de fuga estimada y las fugas medidas de forma real, información confidencial puede ser reconstruida en mucho menos tiempo y computación. Para ser precisos, SCA básicamente cubre una amplia gama de tipos de ataques, como los análisis de consumo de energía y radiación ElectroMagnética (EM). Ambos se basan en análisis estadístico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no están intrínsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementación de circuitos integrar medidas que permitan camuflar las fugas a través de "canales laterales". Las medidas contra SCA están evolucionando junto con el desarrollo de nuevas técnicas de ataque, así como la continua mejora de los dispositivos electrónicos. Las características físicas requieren contramedidas sobre la capa física, que generalmente se pueden clasificar en soluciones intrínsecas y extrínsecas. Contramedidas extrínsecas se ejecutan para confundir la fuente de ataque mediante la integración de ruido o mala alineación de la actividad interna. Comparativamente, las contramedidas intrínsecas están integradas en el propio algoritmo, para modificar la aplicación con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultación y Enmascaramiento son dos técnicas típicas incluidas en esta categoría. Concretamente, el enmascaramiento se aplica a nivel algorítmico, para alterar los datos intermedios sensibles con una máscara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptografías modernas son difíciles de enmascarar. Dicho método de ocultación, que ha sido verificado como una solución efectiva, comprende principalmente la codificación en doble carril, que está ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, además de la descripción de las metodologías de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la lógica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel lógico. Una característica de SCA reside en el formato de las fuentes de fugas. Un típico ataque de canal lateral se refiere al análisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades parásitas son las fuentes esenciales de fugas. Por lo tanto, una lógica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas lógicas básicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la lógica desde un nivel más alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones clásicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementación de un esquema de diseño personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el diseño y la implementación de una lógica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener dinámicamente el equilibrio de las fugas en las capas inferiores; II. Esta lógica explota las características de la arquitectura de las FPGAs, para reducir al mínimo el gasto de recursos en la implementación; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo genérico de diseño sobre FPGAs, con el fin de manipular los circuitos de forma automática. El kit de herramientas de diseño automático es compatible con la lógica de doble carril propuesta, para facilitar la aplicación práctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodología y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho más rígidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementación y reparación de lógica de doble carril genérica. La viabilidad de las soluciones propuestas es validada mediante la selección de algoritmos criptográficos ampliamente utilizados, y su evaluación exhaustiva en comparación con soluciones anteriores. Todas las propuestas están respaldadas eficazmente a través de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigación tiene la intención de cerrar la brecha entre las barreras de implementación y la aplicación efectiva de lógica de doble carril. En esencia, a lo largo de esta tesis se describirá un conjunto de herramientas de implementación para FPGAs que se han desarrollado para trabajar junto con el flujo de diseño genérico de las mismas, con el fin de lograr crear de forma innovadora la lógica de doble carril. Un nuevo enfoque en el ámbito de la seguridad en el cifrado se propone para obtener personalización, automatización y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigación se resumen brevemente a continuación: Lógica de Precharge Absorbed-DPL logic: El uso de la conversión de netlist para reservar LUTs libres para ejecutar la señal de precharge y Ex en una lógica DPL. Posicionamiento entrelazado Row-crossed con pares idénticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medición EM selectiva y mitigar los impactos de las variaciones de proceso. Ejecución personalizada y herramientas de conversión automática para la generación de redes idénticas para la lógica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asimétricas. (c) Para ser utilizado en otras lógicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. Plataforma CPA de pruebas personalizadas para el análisis de EM y potencia, incluyendo la construcción de dicha plataforma, el método de medición y análisis de los ataques. Análisis de tiempos para cuantificar los niveles de seguridad. División de Seguridad en la conversión parcial de un sistema de cifrado complejo para reducir los costes de la protección. Prueba de concepto de un sistema de calefacción auto-adaptativo para mitigar los impactos eléctricos debido a la variación del proceso de silicio de manera dinámica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuación: En el capítulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos básicos de teoría de modelos de análisis, además de la implementación de la plataforma y la ejecución de los ataques. En el capítulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Además de ello, en este capítulo se propone una lógica en doble carril compacta y segura como contribución de gran relevancia, así como también se presentará la transformación lógica basada en un diseño a nivel de puerta. Por otra parte, en el Capítulo 3 se abordan los desafíos relacionados con la implementación de lógica en doble carril genérica. Así mismo, se describirá un flujo de diseño personalizado para resolver los problemas de aplicación junto con una herramienta de desarrollo automático de aplicaciones propuesta, para mitigar las barreras de diseño y facilitar los procesos. En el capítulo 4 se describe de forma detallada la elaboración e implementación de las herramientas propuestas. Por otra parte, la verificación y validaciones de seguridad de la lógica propuesta, así como un sofisticado experimento de verificación de la seguridad del rutado, se describen en el capítulo 5. Por último, un resumen de las conclusiones de la tesis y las perspectivas como líneas futuras se incluyen en el capítulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada capítulo se describe de forma más detallada a continuación: En el capítulo 1 se introduce plataforma de implementación hardware además las teorías básicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura genérica y las características de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un módulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los métodos de canal lateral, que permiten revelar las fugas de disipación correlacionadas con los comportamientos internos; y el método para recuperar esta relación entre las fluctuaciones físicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del capítulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protección de la compensación dinámica de la lógica genérica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripción de los elementos compensados a nivel de puerta. En segundo lugar, la lógica PA-DPL es propuesta como aportación original, detallando el protocolo de la lógica y un caso de aplicación. En tercer lugar, dos flujos de diseño personalizados se muestran para realizar la conversión de doble carril. Junto con ello, se aclaran las definiciones técnicas relacionadas con la manipulación por encima de la netlist a nivel de LUT. Finalmente, una breve discusión sobre el proceso global se aborda en la parte final del capítulo. El Capítulo 3 estudia los principales retos durante la implementación de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantación a través de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos parásitos, sesgo tecnológico y la viabilidad de implementación. De acuerdo con estas elaboraciones, se plantean dos problemas: Cómo implementar la lógica propuesta sin penalizar los niveles de seguridad, y cómo manipular un gran número de celdas y automatizar el proceso. El PA-DPL propuesto en el capítulo 2 se valida con una serie de iniciativas, desde características estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los métodos de aplicación tales como las herramientas de personalización y automatización de EDA. Por otra parte, un sistema de calefacción auto-adaptativo es representado y aplicado a una lógica de doble núcleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variación del proceso durante la operación en tiempo real. El capítulo 4 se centra en los detalles de la implementación del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la lógica de circuito post P&R ncd (una versión binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y razón de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detección de enrutamiento y los enfoques para la reparación. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente idénticos para la lógica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este capítulo particularmente especifica las bases técnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El capítulo 5 se enfoca en la aplicación de los casos de estudio para la validación de los grados de seguridad de la lógica propuesta. Se discuten los problemas técnicos detallados durante la ejecución y algunas nuevas técnicas de implementación. (a) Se discute el impacto en el proceso de posicionamiento de la lógica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementación, tomando en cuenta la optimización global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparación optimizados; (b) las validaciones de seguridad se realizan con los métodos de correlación y análisis de tiempo; (c) Una táctica asintótica se aplica a un núcleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre métricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacción auto-adaptativa sobre la variación del proceso son mostrados; (e) Se introduce una aplicación práctica de las herramientas para un diseño de cifrado completa. Capítulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por último, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilización de las contribuciones de esta tesis a un alcance más allá de los dominios de la criptografía en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. A timing analysis based method for quantifying the security grades. A methodology of security partitions of complex crypto systems for reducing the protection cost. A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Análisis de la influencia del régimen de neutro en la compatibilidad electromagnética en edificios hospitalarios y propuesta de una nueva técnica correctora

La presente tesis aborda el estudio de los distintos regímenes de neutro de las instalaciones de baja tensión, comúnmente llamados sistemas de puesta a tierra, desde un doble punto de vista, con el objetivo final de establecer un estándar justificado para un posterior desarrollo normativo, y de diseño que facilite la operación y funcionamiento de la instalación eléctrica y de comunicaciones en los sistemas hospitalarios. En una primera parte de la tesis se detallará que aunque hay muchos estudios teórico-prácticos sobre la elección del régimen de neutro en base a criterios operativos y puramente eléctricos, criterios como seguridad frente a accidentes eléctricos, o en términos de disponibilidad, mantenimiento o fiabilidad, esas recomendaciones no se han trasladado de manera directa a la legislación española salvo en el caso de Salas de Intervención donde se obliga a un sistema IT. Por eso se justificará como una primera técnica correctora de un inadecuado funcionamiento electromagnético en Hospitales el establecer una propuesta de marco normativo donde se fijen los tipos de puesta a tierra en función del uso y tipología del edificio desde un punto de vista eléctrico Por otra parte, la influencia de los distintos regímenes de neutro en la transmisión de señales (compatibilidad magnética) no ha sido estudiada en toda su profundidad, no existiendo ni marco normativo obligado ni estudios en profundidad sobre estas afecciones. Por tanto y en una segunda parte de la tesis se propondrá como medida correctora para mejorar el funcionamiento electromagnético de un hospital qué el régimen de neutro TN-S es más respetuoso con el funcionamiento de los equipos de electromedicina que alberga en su interior, estableciendo así mismo una propuesta de norma que regule este diseño. En definitiva se justifica que es posible generar por diseño inicial de la red eléctrica, mediante un régimen de neutro TN-S, un contexto electromagnético óptimo para el funcionamiento del sistema hospitalario que no se logra con otras opciones contempladas en la normativa española. ABSTRACT This thesis deals with the study of various ground grid systems of low voltage installations, commonly called grounding systems, from two points of view, with the ultimate goal of establishing a standard justified from a policy perspective and design to facilitate the operation and functioning of the electrical system and hospital communications systems. In the first part of the thesis will be detailed that although there are many theoretical and practical studies on the choice of the neutral system based on operational criteria and purely electric, criteria such as safety against electrical accidents, or in terms of availability, maintenance and reliability, these recommendations have not been transferred directly to the Spanish legislation except in Intervention Rooms where a IT system is required. So be justified as a first corrective technique improper operation electromagnetic Hospitals proposal to establish a regulatory framework where ground types depending on the use and type of building are set from an electrical point of view . Moreover, the influence of the different regimes neutral signaling (magnetic compatibility) has not been studied in any depth, there being neither forced nor depth studies on these conditions regulatory framework. Thus in a second part of the thesis will be justified as a corrective measure to improve the electromagnetic performance of a hospital which the neutral TN-S is more respectful of the performance of medical electrical equipment housed in its interior, thus establishing same a proposed rule governing this design. Ultimately it is possible to generate justified by initial design of the grid, using a neutral system TN-S, electromagnetic optimal context for the operation of the hospital system is not achieved with other legal options in Spain.

Broadband active differential array for the mid-frequency SKA band

This paper presents the design and characterization process of an active array demonstrator for the mid-frequency range (i.e., 300 MHz-1000 MHz) of the future Square Kilometre Array (SKA) radio telescope. This demonstrator, called FIDA3 (FG-IGN: Fundación General Instituto Geográfico Nacional - Differential Active Antenna Array), is part of the Spanish contribution for the SKA project. The main advantages provided by this design include the use of a dielectric-free structure, and the use of a fully-differential receiver in which differential low-noise amplifiers (LNAs) are directly connected to the balanced tapered-slot antennas (TSAs). First, the radiating structure and the differential low-noise amplifiers were separately designed and measured, obtaining good results (antenna elements with low voltage standing-wave ratios, array scanning capabilities up to 45°, and noise temperatures better than 52 K with low-noise amplifiers at room temperature). The potential problems due to the differential nature of the proposed solution are discussed, so some effective methods to overcome such limitations are proposed. Second, the complete active antenna array receiving system was assembled, and a 1 m2 active antenna array tile was characterized.

Modal liquid crystal microaxicon array

A novel tunable liquid crystal microaxicon array is proposed and experimentally demonstrated. The proposed structure is capable of generating tunable axicons (thousands of elements) of micrometric size, with simple control (four control voltages) and low voltage, and is totally reconfigurable. Depending on the applied voltages, control over the diameter, as well as the effective wedge angle, can be achieved. Controls over the diameter ranging from 107 to 77 μm have been demonstrated. In addition, a control over the phase profile tunability, from 12π to 24π radians, has been demonstrated. This result modifies the effective cone angle. The diameter tunability, as well the effective cone angle, results in a control over the nondiffractive Bessel beam distance. The RMS wavefront deviation from the ideal axicon is only λ∕3. The proposed device has several advantages over the existing microaxicon arrays, including being simple having a low cost. The device could contribute to developing new applications and to reducing the fabrication costs of current devices.