Thin film shape memory alloys for optical sensing applications

Based on shape memory effect of the sputtered thin film shape memory alloys, different types of micromirror structures were designed and fabricated for optical sensing application. Using surface micromachining, TiNi membrane mirror structure has been fabricated, which can be actuated based on intrinsic two-way shape memory effect of the free-standing TiNi film. Using bulk micromachining, TiNi/Si and TiNi/Si 3N 4microcantilever mirror structures were fabricated. © 2007 IOP Publishing Ltd.

Thin film shape memory alloys and microactuators

For Micro-electro-mechanical System (MEMS) applications, TiNi-based thin film Shape Memory Alloys (SMAs) possess many desirable properties, such as high power density, large transformation stress and strain upon heating and cooling, superelasticity and biocompatibility. In this paper, recent development in TiNi-based thin film SMA and microactuator applications is discussed. The topics related to film deposition and characterisation is mainly focused on crystal nucleation and growth during annealing, film thickness effect, film texture, stress induced surface relief, wrinkling and trenches as well as Temperature Memory Effect (TME). The microactuator applications are mainly focused on microvalve and microcage for biological applications, micromirror for optical applications and data storage using nanoindentation method. Copyright © 2009, Inderscience Publishers.

Floating-body SOI memory: Concepts, physics and challenges

We present an overview of the single-transistor memory cells (lT-DRAMs), which are based on floating-body effects in SOI MOSFETs. The typical device architectures, principles of operation and key mechanisms for programming are described. The various approaches (Z-RAM, MSDRAM, etc) are compared in terms of performance and potential for aggressive scaling. ©The Electrochemical Society.

Long-term exposure to extremely low-frequency magnetic fields impairs spatial recognition memory in mice

1. In the present study, we investigated the short- and long-term effects of extremely low-frequency (ELF) magnetic fields on spatial recognition memory in mice by using a two-trial recognition Y-maze that is based on the innate tendency of rodents to exp

SIMPLE REMESHING SCHEME FOR THE FINITE ELEMENT BASED SIMULATION OF DOPANT DIFFUSION IN SILICON.

Process simulation programs are valuable in generating accurate impurity profiles. Apart from accuracy the programs should also be efficient so as not to consume vast computer memory. This is especially true for devices and circuits of VLSI complexity. In this paper a remeshing scheme to make the finite element based solution of the non-linear diffusion equation more efficient is proposed. A remeshing scheme based on comparing the concentration values of adjacent node was then implemented and found to remove the problems of oscillation.

Improved switching uniformity and low-voltage operation in TaO x-based RRAM using Ge reactive layer

Significant improvements in the spatial and temporal uniformities of device switching parameters are successfully demonstrated in Ge/TaOx bilayer-based resistive switching devices, as compared with non-Ge devices. In addition, the reported Ge/TaOx devices also show significant reductions in the operation voltages. Influence of the Ge layer on the resistive switching of TaOx-based resistive random access memory is investigated by X-ray spectroscopy and the theory of Gibbs free energy. Higher uniformity is attributed to the confinement of the filamentary switching process. The presence of a larger number of interface traps, which will create a beneficial electric field to facilitate the drift of oxygen vacancies, is believed to be responsible for the lower operation voltages in the Ge/TaO x devices. © 1980-2012 IEEE.

"Plateau"-related summary statistics are uninformative for comparing working memory models.

Performance on visual working memory tasks decreases as more items need to be remembered. Over the past decade, a debate has unfolded between proponents of slot models and slotless models of this phenomenon (Ma, Husain, Bays (Nature Neuroscience 17, 347-356, 2014). Zhang and Luck (Nature 453, (7192), 233-235, 2008) and Anderson, Vogel, and Awh (Attention, Perception, Psychophys 74, (5), 891-910, 2011) noticed that as more items need to be remembered, "memory noise" seems to first increase and then reach a "stable plateau." They argued that three summary statistics characterizing this plateau are consistent with slot models, but not with slotless models. Here, we assess the validity of their methods. We generated synthetic data both from a leading slot model and from a recent slotless model and quantified model evidence using log Bayes factors. We found that the summary statistics provided at most 0.15 % of the expected model evidence in the raw data. In a model recovery analysis, a total of more than a million trials were required to achieve 99 % correct recovery when models were compared on the basis of summary statistics, whereas fewer than 1,000 trials were sufficient when raw data were used. Therefore, at realistic numbers of trials, plateau-related summary statistics are highly unreliable for model comparison. Applying the same analyses to subject data from Anderson et al. (Attention, Perception, Psychophys 74, (5), 891-910, 2011), we found that the evidence in the summary statistics was at most 0.12 % of the evidence in the raw data and far too weak to warrant any conclusions. The evidence in the raw data, in fact, strongly favored the slotless model. These findings call into question claims about working memory that are based on summary statistics.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

Observation of N-Shaped Negative Differential Resistance in GaAs-Based Modulation-Doped Field Effect Transistor with InAs Quantum Dots

N-shaped negative differential resistance (NDR) with a high peak-to-valley ratio (PVR) is observed in a GaAs-based modulation-doped field effect transistor (MODFET) with InAs quantum dots (QDs) in the barrier layer (QDFET) compared with a GaAs MODFET. The NDR is explained as the real-space transfer (RST) of high-mobility electrons in a channel into nearby barrier layers with low mobility, and the PVR is enhanced dramatically upon inserting the QD layer. It is also revealed that the QD layer traps holes and acts as a positively charged nano-floating gate after a brief optical illumination, while it acts as a negatively charged nano-floating gate and depletes the adjacent channel when charged by the electrons. The NDR suggests a promising application in memory or high-speed logic devices for the QDFET structure.

Electrical bistability and negative differential resistance in diodes based on silver nanoparticle-poly(N-vinylcarbazole) composites

An electrically bistable device has been fabricated using nanocomposite films consisting of silver nanoparticles and a semiconducting polymer by a simple spin-coating method. The current-voltage characteristics of the as-fabricated devices exhibit an obvious electrical bistability and negative differential resistance effect. The current ratio between the high-conducting state and low-conducting state can reach more than 103 at room temperature. The electrical bistability of the device is attributed to the electric-filed-induced charge transfer between the silver nanoparticles and the polymer, and the negative differential resistance behavior is related to the charge trapping in the silver nanoparticles. The results open up a simple approach to fabricate high quality electrically bistable devices by doping metal nanoparticles into polymer.

The morphology control of pentacene for write-once-read-many-times memory devices

We realized write-once-read-many-times (WORM) memory devices based on pentacene and demonstrated that the morphology control of the vacuum deposited pentacene thin film is greatly important for achieving the unique nonvolatile memory properties. The resulted memory devices show a high ON/OFF current ratio (10(4)), long retention time (over 12 h), and good storage stability (over 240 h). The reduction of the barrier height caused by a large interface dipole and the damage of the interface dipole under a critical bias voltage have been used to explain the transition processes.

Realization of negative differential resistance and switching devices based on copper phthalocyanine by the control of evaporation rate

We have observed, respectively, a negative differential resistance (NDR) and switching conduction in current-voltage (I-V) characteristics of organic diodes based on copper phthalocyanine (CuPc) film sandwiched between indium-tin-oxide (ITO) and aluminum (Al) by controlling the evaporation rate. The NDR effect is repeatable which can be well, controlled by sweep rate and start voltage, and the switching exhibits write-once-read-many-times (WORM) memory characteristics. The traps in the organic layer and interfacial dipole have been used to explain the NDR effect and switching conduction. This opens up potential applications for CuPc organic semiconductor in low power memory and logic circuits.

Negative differential resistance effect in organic devices based on an anthracene derivative

The authors observed a negative differential resistance (NDR) in organic devices consisting of 9,10-bis-(9,9-diphenyl-9H-fluoren-2-yl)-anthracene (DPFA) sandwiched between Ag and indium tin oxide electrodes. The large NDR shown in current-voltage characteristics is reproducible, resulting in that the organic devices can be electrically switched between a high conductance state (on state) and a low conductance state (off state). It can be found that the currents at both on to off states are space-charge limited and attributed to the electron traps at the Ag/DPFA interface. The large and reproducible NDR makes the devices of tremendous potential in low power memory and logic circuits.

Negative differential resistance and multilevel memory effects in organic devices

Negative differential resistance ( NDR) and multilevel memory effects were obtained in organic devices consisting of an anthracene derivative, 9,10-bis-{ 9,9-di-[ 4-(phenyl-p-tolyl-amino)-phenyl]-9H-fluoren-2-yl}-anthracene ( DAFA), sandwiched between Ag and ITO electrodes. The application of a negative bias voltage leads to negative differential resistance in current-voltage characteristics and different negative voltages produce different conductance currents, resulting in the multilevel memory capability of the devices. The NDR property has been attributed to charge trapping at the DAFA/Ag interface. This opens up a wide range of application possibilities of such organic-based NDR devices in memory and logic circuits.

A Lifetime-based Garbage Collector for LISP Systems on General-Purpose Computers

Garbage collector performance in LISP systems on custom hardware has been substantially improved by the adoption of lifetime-based garbage collection techniques. To date, however, successful lifetime-based garbage collectors have required special-purpose hardware, or at least privileged access to data structures maintained by the virtual memory system. I present here a lifetime-based garbage collector requiring no special-purpose hardware or virtual memory system support, and discuss its performance.