Write-Once Read-Many-Times Memory Based on a Single Layer of Pentacene

We realized an organic electrical memory device with a simple structure based on single-layer pentacene film embedded between Al and ITO electrodes. The optimization of the thickness and deposition rate of pentacene resulted in a reliable device with an on/off current ratio as high as nearly 10(6), which was two orders of magnitude higher than previous results, and the storage time was more than 576 h. The current transition process is attributed to the formation and damage of the Interface dipole at different electric fields, in which the current conduction showed a transition from ohmic conductive current to Fowler-Nordheim tunneling current. After the transition from ON- to OFF-state, the device tended to remain in the OFF-State even when the applied voltage was removed, which indicated that the device was very promising for write-once read-many-times memory.

Nonvolatile memory devices based on gold nanoparticle and poly (N-Vinylcarbazole) composite

A rewritable polymer memory device based on gold nanoparticle doped poly (N-vinylcarbazole) (PVK), which can be easily fabricated by simple spin coating, has been described. An electrical bistable phenomenon is observed in the current-voltage characteristics of this device, and it is found that the electrical bistability is repeatable by proper writing voltage and erasing voltage. The unique behavior of the devices provides an interesting approach such that doping nanoparticles in polymer can be used to realize high performance nanovolatile polymer memory devices.

A Parallel Crossbar Routing Chip for a Shared Memory Multiprocessor

This thesis describes the design and implementation of an integrated circuit and associated packaging to be used as the building block for the data routing network of a large scale shared memory multiprocessor system. A general purpose multiprocessor depends on high-bandwidth, low-latency communications between computing elements. This thesis describes the design and construction of RN1, a novel self-routing, enhanced crossbar switch as a CMOS VLSI chip. This chip provides the basic building block for a scalable pipelined routing network with byte-wide data channels. A series of RN1 chips can be cascaded with no additional internal network components to form a multistage fault-tolerant routing switch. The chip is designed to operate at clock frequencies up to 100Mhz using Hewlett-Packard's HP34 $1.2\\mu$ process. This aggressive performance goal demands that special attention be paid to optimization of the logic architecture and circuit design.

Mermera: Non-Coherent Distributed Shared Memory for Parallel Computing

The proliferation of inexpensive workstations and networks has prompted several researchers to use such distributed systems for parallel computing. Attempts have been made to offer a shared-memory programming model on such distributed memory computers. Most systems provide a shared-memory that is coherent in that all processes that use it agree on the order of all memory events. This dissertation explores the possibility of a significant improvement in the performance of some applications when they use non-coherent memory. First, a new formal model to describe existing non-coherent memories is developed. I use this model to prove that certain problems can be solved using asynchronous iterative algorithms on shared-memory in which the coherence constraints are substantially relaxed. In the course of the development of the model I discovered a new type of non-coherent behavior called Local Consistency. Second, a programming model, Mermera, is proposed. It provides programmers with a choice of hierarchically related non-coherent behaviors along with one coherent behavior. Thus, one can trade-off the ease of programming with coherent memory for improved performance with non-coherent memory. As an example, I present a program to solve a linear system of equations using an asynchronous iterative algorithm. This program uses all the behaviors offered by Mermera. Third, I describe the implementation of Mermera on a BBN Butterfly TC2000 and on a network of workstations. The performance of a version of the equation solving program that uses all the behaviors of Mermera is compared with that of a version that uses coherent behavior only. For a system of 1000 equations the former exhibits at least a 5-fold improvement in convergence time over the latter. The version using coherent behavior only does not benefit from employing more than one workstation to solve the problem while the program using non-coherent behavior continues to achieve improved performance as the number of workstations is increased from 1 to 6. This measurement corroborates our belief that non-coherent shared memory can be a performance boon for some applications.

An Implementation of Mermera: A Shared Memory System that Mixes Coherence with Non-coherence

Coherent shared memory is a convenient, but inefficient, method of inter-process communication for parallel programs. By contrast, message passing can be less convenient, but more efficient. To get the benefits of both models, several non-coherent memory behaviors have recently been proposed in the literature. We present an implementation of Mermera, a shared memory system that supports both coherent and non-coherent behaviors in a manner that enables programmers to mix multiple behaviors in the same program[HS93]. A programmer can debug a Mermera program using coherent memory, and then improve its performance by selectively reducing the level of coherence in the parts that are critical to performance. Mermera permits a trade-off of coherence for performance. We analyze this trade-off through measurements of our implementation, and by an example that illustrates the style of programming needed to exploit non-coherence. We find that, even on a small network of workstations, the performance advantage of non-coherence is compelling. Raw non-coherent memory operations perform 20-40~times better than non-coherent memory operations. An example application program is shown to run 5-11~times faster when permitted to exploit non-coherence. We conclude by commenting on our use of the Isis Toolkit of multicast protocols in implementing Mermera.

Communicable Memory and Lazy Barriers for Bulk Synchronous Parallelism in BSPk

Communication and synchronization stand as the dual bottlenecks in the performance of parallel systems, and especially those that attempt to alleviate the programming burden by incurring overhead in these two domains. We formulate the notions of communicable memory and lazy barriers to help achieve efficient communication and synchronization. These concepts are developed in the context of BSPk, a toolkit library for programming networks of workstations|and other distributed memory architectures in general|based on the Bulk Synchronous Parallel (BSP) model. BSPk emphasizes efficiency in communication by minimizing local memory-to-memory copying, and in barrier synchronization by not forcing a process to wait unless it needs remote data. Both the message passing (MP) and distributed shared memory (DSM) programming styles are supported in BSPk. MP helps processes efficiently exchange short-lived unnamed data values, when the identity of either the sender or receiver is known to the other party. By contrast, DSM supports communication between processes that may be mutually anonymous, so long as they can agree on variable names in which to store shared temporary or long-lived data.

Admission Control and Scheduling for High-Performance WWW Servers

In this paper we examine a number of admission control and scheduling protocols for high-performance web servers based on a 2-phase policy for serving HTTP requests. The first "registration" phase involves establishing the TCP connection for the HTTP request and parsing/interpreting its arguments, whereas the second "service" phase involves the service/transmission of data in response to the HTTP request. By introducing a delay between these two phases, we show that the performance of a web server could be potentially improved through the adoption of a number of scheduling policies that optimize the utilization of various system components (e.g. memory cache and I/O). In addition, to its premise for improving the performance of a single web server, the delineation between the registration and service phases of an HTTP request may be useful for load balancing purposes on clusters of web servers. We are investigating the use of such a mechanism as part of the Commonwealth testbed being developed at Boston University.

On the Performance and Robustness of Managing Reliable Transport Connections

We revisit the problem of connection management for reliable transport. At one extreme, a pure soft-state (SS) approach (as in Delta-t [9]) safely removes the state of a connection at the sender and receiver once the state timers expire without the need for explicit removal messages. And new connections are established without an explicit handshaking phase. On the other hand, a hybrid hard-state/soft-state (HS+SS) approach (as in TCP) uses both explicit handshaking as well as timer-based management of the connection’s state. In this paper, we consider the worst-case scenario of reliable single-message communication, and develop a common analytical model that can be instantiated to capture either the SS approach or the HS+SS approach. We compare the two approaches in terms of goodput, message and state overhead. We also use simulations to compare against other approaches, and evaluate them in terms of correctness (with respect to data loss and duplication) and robustness to bad network conditions (high message loss rate and variable channel delays). Our results show that the SS approach is more robust, and has lower message overhead. On the other hand, SS requires more memory to keep connection states, which reduces goodput. Given memories are getting bigger and cheaper, SS presents the best choice over bandwidth-constrained, error-prone networks.

An Efficient User-Level Shared Memory Mechanism for Application-Specific Extensions

This paper focuses on an efficient user-level method for the deployment of application-specific extensions, using commodity operating systems and hardware. A sandboxing technique is described that supports multiple extensions within a shared virtual address space. Applications can register sandboxed code with the system, so that it may be executed in the context of any process. Such code may be used to implement generic routines and handlers for a class of applications, or system service extensions that complement the functionality of the core kernel. Using our approach, application-specific extensions can be written like conventional user-level code, utilizing libraries and system calls, with the advantage that they may be executed without the traditional costs of scheduling and context-switching between process-level protection domains. No special hardware support such as segmentation or tagged translation look-aside buffers (TLBs) is required. Instead, our ``user-level sandboxing'' mechanism requires only paged-based virtual memory support, given that sandboxed extensions are either written by a trusted source or are guaranteed to be memory-safe (e.g., using type-safe languages). Using a fast method of upcalls, we show how our mechanism provides significant performance improvements over traditional methods of invoking user-level services. As an application of our approach, we have implemented a user-level network subsystem that avoids data copying via the kernel and, in many cases, yields far greater network throughput than kernel-level approaches.

Cuckoo: a Language for Implementing Memory- and Thread-safe System Services

This paper is centered around the design of a thread- and memory-safe language, primarily for the compilation of application-specific services for extensible operating systems. We describe various issues that have influenced the design of our language, called Cuckoo, that guarantees safety of programs with potentially asynchronous flows of control. Comparisons are drawn between Cuckoo and related software safety techniques, including Cyclone and software-based fault isolation (SFI), and performance results suggest our prototype compiler is capable of generating safe code that executes with low runtime overheads, even without potential code optimizations. Compared to Cyclone, Cuckoo is able to safely guard accesses to memory when programs are multithreaded. Similarly, Cuckoo is capable of enforcing memory safety in situations that are potentially troublesome for techniques such as SFI.

The impact of anxiety-inducing distraction on cognitive performance: a combined brain imaging and personality investigation.

BACKGROUND: Previous investigations revealed that the impact of task-irrelevant emotional distraction on ongoing goal-oriented cognitive processing is linked to opposite patterns of activation in emotional and perceptual vs. cognitive control/executive brain regions. However, little is known about the role of individual variations in these responses. The present study investigated the effect of trait anxiety on the neural responses mediating the impact of transient anxiety-inducing task-irrelevant distraction on cognitive performance, and on the neural correlates of coping with such distraction. We investigated whether activity in the brain regions sensitive to emotional distraction would show dissociable patterns of co-variation with measures indexing individual variations in trait anxiety and cognitive performance. METHODOLOGY/PRINCIPAL FINDINGS: Event-related fMRI data, recorded while healthy female participants performed a delayed-response working memory (WM) task with distraction, were investigated in conjunction with behavioural measures that assessed individual variations in both trait anxiety and WM performance. Consistent with increased sensitivity to emotional cues in high anxiety, specific perceptual areas (fusiform gyrus--FG) exhibited increased activity that was positively correlated with trait anxiety and negatively correlated with WM performance, whereas specific executive regions (right lateral prefrontal cortex--PFC) exhibited decreased activity that was negatively correlated with trait anxiety. The study also identified a role of the medial and left lateral PFC in coping with distraction, as opposed to reflecting a detrimental impact of emotional distraction. CONCLUSIONS: These findings provide initial evidence concerning the neural mechanisms sensitive to individual variations in trait anxiety and WM performance, which dissociate the detrimental impact of emotion distraction and the engagement of mechanisms to cope with distracting emotions. Our study sheds light on the neural correlates of emotion-cognition interactions in normal behaviour, which has implications for understanding factors that may influence susceptibility to affective disorders, in general, and to anxiety disorders, in particular.

Sikh Sabad Kirtan as a Musical Construction of Memory

The performance of devotional music in India has been an active, sonic conduit where spiritual identities are shaped and forged, and both history and mythology lived out and remembered daily. For the followers of Sikhism, congregational hymn singing has been the vehicle through which text, melody and ritual act as repositories of memory, elevating memory to a place where historical and social events can be reenacted and memorialized on levels of spiritual significance. This dissertation investigates the musical process of Shabad Kirtan, Sikh hymn singing, in a Sikh musical service as a powerful vehicle to forge a sense of identification between individual and the group. As an intimate part of Sikh life from birth to death, the repertoire of Shabad Kirtan draws from a rich mosaic of classical and folk genres as well as performance styles, acting as a musical and cognitive archive. Through a detailed analysis of the Asa Di Var service, Shabad Kirtan is explored as a phenomenological experience where time, place and occasion interact as a meaningful unit through which the congregation creates and recreates themselves, invoking deep memories and emotional experiences. Supported by explanatory tables, diagrams and musical transcriptions, the sonic movements of the service show how the Divine Word as Shabad is not only embodied through the Guru Granth Sahib, but also encountered through the human enactment of the service, aurally, viscerally and phenomenologically.

Imagery and retrieval of auditory and visual information: neural correlates of successful and unsuccessful performance.

Remembering past events - or episodic retrieval - consists of several components. There is evidence that mental imagery plays an important role in retrieval and that the brain regions supporting imagery overlap with those supporting retrieval. An open issue is to what extent these regions support successful vs. unsuccessful imagery and retrieval processes. Previous studies that examined regional overlap between imagery and retrieval used uncontrolled memory conditions, such as autobiographical memory tasks, that cannot distinguish between successful and unsuccessful retrieval. A second issue is that fMRI studies that compared imagery and retrieval have used modality-aspecific cues that are likely to activate auditory and visual processing regions simultaneously. Thus, it is not clear to what extent identified brain regions support modality-specific or modality-independent imagery and retrieval processes. In the current fMRI study, we addressed this issue by comparing imagery to retrieval under controlled memory conditions in both auditory and visual modalities. We also obtained subjective measures of imagery quality allowing us to dissociate regions contributing to successful vs. unsuccessful imagery. Results indicated that auditory and visual regions contribute both to imagery and retrieval in a modality-specific fashion. In addition, we identified four sets of brain regions with distinct patterns of activity that contributed to imagery and retrieval in a modality-independent fashion. The first set of regions, including hippocampus, posterior cingulate cortex, medial prefrontal cortex and angular gyrus, showed a pattern common to imagery/retrieval and consistent with successful performance regardless of task. The second set of regions, including dorsal precuneus, anterior cingulate and dorsolateral prefrontal cortex, also showed a pattern common to imagery and retrieval, but consistent with unsuccessful performance during both tasks. Third, left ventrolateral prefrontal cortex showed an interaction between task and performance and was associated with successful imagery but unsuccessful retrieval. Finally, the fourth set of regions, including ventral precuneus, midcingulate cortex and supramarginal gyrus, showed the opposite interaction, supporting unsuccessful imagery, but successful retrieval performance. Results are discussed in relation to reconstructive, attentional, semantic memory, and working memory processes. This is the first study to separate the neural correlates of successful and unsuccessful performance for both imagery and retrieval and for both auditory and visual modalities.

Inhibition-Induced Forgetting Results from Resource Competition between Response Inhibition and Memory Encoding Processes.

UNLABELLED: Response inhibition is a key component of executive control, but its relation to other cognitive processes is not well understood. We recently documented the "inhibition-induced forgetting effect": no-go cues are remembered more poorly than go cues. We attributed this effect to central-resource competition, whereby response inhibition saps attention away from memory encoding. However, this proposal is difficult to test with behavioral means alone. We therefore used fMRI in humans to test two neural predictions of the "common resource hypothesis": (1) brain regions associated with response inhibition should exhibit greater resource demands during encoding of subsequently forgotten than remembered no-go cues; and (2) this higher inhibitory resource demand should lead to memory encoding regions having less resources available during encoding of subsequently forgotten no-go cues. Participants categorized face stimuli by gender in a go/no-go task and, following a delay, performed a surprise recognition memory test for those faces. Replicating previous findings, memory was worse for no-go than for go stimuli. Crucially, forgetting of no-go cues was predicted by high inhibitory resource demand, as quantified by the trial-by-trial ratio of activity in neural "no-go" versus "go" networks. Moreover, this index of inhibitory demand exhibited an inverse trial-by-trial relationship with activity in brain regions responsible for the encoding of no-go cues into memory, notably the ventrolateral prefrontal cortex. This seesaw pattern between the neural resource demand of response inhibition and activity related to memory encoding directly supports the hypothesis that response inhibition temporarily saps attentional resources away from stimulus processing. SIGNIFICANCE STATEMENT: Recent behavioral experiments showed that inhibiting a motor response to a stimulus (a "no-go cue") impairs subsequent memory for that cue. Here, we used fMRI to test whether this "inhibition-induced forgetting effect" is caused by competition for neural resources between the processes of response inhibition and memory encoding. We found that trial-by-trial variations in neural inhibitory resource demand predicted subsequent forgetting of no-go cues and that higher inhibitory demand was furthermore associated with lower concurrent activation in brain regions responsible for successful memory encoding of no-go cues. Thus, motor inhibition and stimulus encoding appear to compete with each other: when more resources have to be devoted to inhibiting action, less are available for encoding sensory stimuli.

A scalable strategy for the parallelization of multiphysics unstructured mesh-iterative codes on distributed-memory systems

Realizing scalable performance on high performance computing systems is not straightforward for single-phenomenon codes (such as computational fluid dynamics [CFD]). This task is magnified considerably when the target software involves the interactions of a range of phenomena that have distinctive solution procedures involving different discretization methods. The problems of addressing the key issues of retaining data integrity and the ordering of the calculation procedures are significant. A strategy for parallelizing this multiphysics family of codes is described for software exploiting finite-volume discretization methods on unstructured meshes using iterative solution procedures. A mesh partitioning-based SPMD approach is used. However, since different variables use distinct discretization schemes, this means that distinct partitions are required; techniques for addressing this issue are described using the mesh-partitioning tool, JOSTLE. In this contribution, the strategy is tested for a variety of test cases under a wide range of conditions (e.g., problem size, number of processors, asynchronous / synchronous communications, etc.) using a variety of strategies for mapping the mesh partition onto the processor topology.