Many-Core Architectures: Hardware-Software Optimization and Modeling Techniques

During the last few decades an unprecedented technological growth has been at the center of the embedded systems design paramount, with Moore���s Law being the leading factor of this trend. Today in fact an ever increasing number of cores can be integrated on the same die, marking the transition from state-of-the-art multi-core chips to the new many-core design paradigm. Despite the extraordinarily high computing power, the complexity of many-core chips opens the door to several challenges. As a result of the increased silicon density of modern Systems-on-a-Chip (SoC), the design space exploration needed to find the best design has exploded and hardware designers are in fact facing the problem of a huge design space. Virtual Platforms have always been used to enable hardware-software co-design, but today they are facing with the huge complexity of both hardware and software systems. In this thesis two different research works on Virtual Platforms are presented: the first one is intended for the hardware developer, to easily allow complex cycle accurate simulations of many-core SoCs. The second work exploits the parallel computing power of off-the-shelf General Purpose Graphics Processing Units (GPGPUs), with the goal of an increased simulation speed. The term Virtualization can be used in the context of many-core systems not only to refer to the aforementioned hardware emulation tools (Virtual Platforms), but also for two other main purposes: 1) to help the programmer to achieve the maximum possible performance of an application, by hiding the complexity of the underlying hardware. 2) to efficiently exploit the high parallel hardware of many-core chips in environments with multiple active Virtual Machines. This thesis is focused on virtualization techniques with the goal to mitigate, and overtake when possible, some of the challenges introduced by the many-core design paradigm.

Piattaforme per Internet of Things: Windows IoT Core come caso di studio

Questa tesi si pone l'obiettivo di esplorare alcuni aspetti di uno dei settori pi�� in crescita in questi anni (e nei prossimi) in ambito informatico: \textbf{Internet of Things}, con un occhio rivolto in particolar modo a quelle che sono le piattaforme di sviluppo disponibili in questo ambito. Con queste premesse, si coglie l'occasione per addentrarsi nella scoperta della piattaforma realizzata e rilasciata da pochi mesi da uno dei colossi del mercato IT: Microsoft. Nel primo capitolo verr�� trattato Internet of Things in ambito generale, attraverso una panoramica iniziale seguita da un'analisi approfondita dei principali protocolli sviluppati per questa tecnologia. Nel secondo capitolo verranno elencate una serie di piattaforme open source disponibili ad oggi per lo sviluppo di sistemi IoT. Dal terzo capitolo verr�� incentrata l'attenzione sulle tecnologie Microsoft, in particolare prima si tratter�� Windows 10 in generale, comprendendo \emph{UWP Applications}. Di seguito, nel medesimo capitolo, sar�� focalizzata l'attenzione su Windows IoT Core, esplorandolo dettagliatamente (Windows Remote Arduino, Modalit�� Headed/Headless, etc.). Il capitolo a seguire concerner�� la parte progettuale della tesi, comprendendo lo sviluppo del progetto \textbf{Smart Parking} in tutte le sue fasi (dei Requisiti fino ad Implementazione e Testing). Nel quinto (ed ultimo) capitolo, saranno esposte le conclusioni relative a Windows IoT Core e i suoi vantaggi/svantaggi.

Robustness of speckle imaging techniques applied to horizontal imaging scenarios

Atmospheric turbulence near the ground severely limits the quality of imagery acquired over long horizontal paths. In defense, surveillance, and border security applications, there is interest in deploying man-portable, embedded systems incorporating image reconstruction methods to compensate turbulence effects. While many image reconstruction methods have been proposed, their suitability for use in man-portable embedded systems is uncertain. To be effective, these systems must operate over significant variations in turbulence conditions while subject to other variations due to operation by novice users. Systems that meet these requirements and are otherwise designed to be immune to the factors that cause variation in performance are considered robust. In addition robustness in design, the portable nature of these systems implies a preference for systems with a minimum level of computational complexity. Speckle imaging methods have recently been proposed as being well suited for use in man-portable horizontal imagers. In this work, the robustness of speckle imaging methods is established by identifying a subset of design parameters that provide immunity to the expected variations in operating conditions while minimizing the computation time necessary for image recovery. Design parameters are selected by parametric evaluation of system performance as factors external to the system are varied. The precise control necessary for such an evaluation is made possible using image sets of turbulence degraded imagery developed using a novel technique for simulating anisoplanatic image formation over long horizontal paths. System performance is statistically evaluated over multiple reconstruction using the Mean Squared Error (MSE) to evaluate reconstruction quality. In addition to more general design parameters, the relative performance the bispectrum and the Knox-Thompson phase recovery methods is also compared. As an outcome of this work it can be concluded that speckle-imaging techniques are robust to the variation in turbulence conditions and user controlled parameters expected when operating during the day over long horizontal paths. Speckle imaging systems that incorporate 15 or more image frames and 4 estimates of the object phase per reconstruction provide up to 45% reduction in MSE and 68% reduction in the deviation. In addition, Knox-Thompson phase recover method is shown to produce images in half the time required by the bispectrum. The quality of images reconstructed using Knox-Thompson and bispectrum methods are also found to be nearly identical. Finally, it is shown that certain blind image quality metrics can be used in place of the MSE to evaluate quality in field scenarios. Using blind metrics rather depending on user estimates allows for reconstruction quality that differs from the minimum MSE by as little as 1%, significantly reducing the deviation in performance due to user action.

Enforcement of the GNU GPL in Germany and Europe

GPL enforcement is successful in Europe. In several court decisions and out of court settlements the license conditions of the GPL have been successfully enforced. In particular, embedded systems are the main focus of such compliance activities. The article describes the practice of enforcement activities and the legal prerequisites under the application of German law.

Extending ASSERT for HW/SW Co-design

Embedded systems are commonly designed by specifying and developing hardware and software systems separately. On the contrary, the hardware/software (HW/SW) co-development exploits the trade-offs between hardware and software in a system through their concurrent design. HW/SW Codevelopment techniques take advantage of the flexibility of system design to create architectures that can meet stringent performance requirements with a shorter design cycle. This paper presents the work done within the scope of ESA HWSWCO (Hardware-Software Co-design) study. The main objective of this study has been to address the HW/SW co-design phase to integrate this engineering task as part of the ASSERT process (refer to [1]) and compatible with the existing ASSERT approach, process and tool, Advances in the automation of the design of HW and SW and the adoption of the Model Driven Architecture (MDA) [9] paradigm make possible the definition of a proper integration substrate and enables the continuous interaction of the HW and SW design paths.

Desarrollo de un datalink con el chip CC1110 de Texas Instruments para UAVs

Se trata de estudiar el comportamiento de un sistema basado en el chip CC1110 de Texas Instruments, para aplicaciones inal��mbricas. Los dispositivos basados en este tipo de chips tienen actualmente gran profusi��n, dada la demanda cada vez mayor de aplicaciones de gesti��n y control inal��mbrico. Por ello, en la primera parte del proyecto se presenta el estado del arte referente a este aspecto, haciendo menci��n a los sistemas operativos embebidos, FPGAs, etc. Tambi��n se realiza una introducci��n sobre la historia de los aviones no tripulados, que son el veh��culo elegido para el uso del enlace de datos. En una segunda parte se realiza el estudio del dispositivo mediante una placa de desarrollo, verificando y comprobando mediante el software suministrado, el alcance del mismo. Cabe resaltar en este punto que el control con la placa mencionada se debe hacer mediante programaci��n de bajo nivel (lenguaje C), lo que aporta gran versatilidad a las aplicaciones que se pueden desarrollar. Por ello, en una tercera parte se realiza un programa funcional, basado en necesidades aportadas por la empresa con la que se colabora en el proyecto (INDRA). Este programa es realizado sobre el entorno de Matlab, muy ��til para este tipo de aplicaciones, dada su versatilidad y gran capacidad de c��lculo con variables. Para terminar, con la realizaci��n de dichos programas, se realizan pruebas espec��ficas para cada uno de ellos, realizando pruebas de campo en algunas ocasiones, con veh��culos los m��s similares a los del entorno real en el que se prev�� utilizar. Como implementaci��n al programa realizado, se incluye un manual de usuario con un formato muy gr��fico, para que la toma de contacto se realice de una manera r��pida y sencilla. Para terminar, se plantean l��neas futuras de aplicaci��n del sistema, conclusiones, presupuesto y un anexo con los c��digos de programaci��n m��s importantes. Abstract In this document studied the system behavior based on chip CC1110 of Texas Instruments, for wireless applications. These devices currently have profusion. Right the increasing demand for control and management wireless applications. In the first part of project presents the state of art of this aspect, with reference to the embedded systems, FPGAs, etc. It also makes a history introduction of UAVs, which are the vehicle for use data link. In the second part is studied the device through development board, verifying and checking with provided software the scope. The board programming is C language; this gives a good versatility to develop applications. Thus, in third part performing a functionally program, it based on requirements provided by company with which it collaborates, INDRA Company. This program is developed with Matlab, very useful for such applications because of its versatility and ability to use variables. Finally, with the implementation of such programs, specific tests are performed for each of them, field tests are performed in several cases, and vehicles used for this are the most similar to the actual environment plain to use. Like implementing with the program made, includes a graphical user manual, so your understanding is conducted quickly and easily. Ultimately, present future targets for system applications, conclusions, budget and annex of the most important programming codes.

Exploration of RVC applications using an ARM multicore processor = Exploraci��n de aplicaciones RVC empleando un procesador ARM multin��cleo

Single core capabilities have reached their maximum clock speed; new multicore architectures provide an alternative way to tackle this issue instead. The design of decoding applications running on top of these multicore platforms and their optimization to exploit all system computational power is crucial to obtain best results. Since the development at the integration level of printed circuit boards are increasingly difficult to optimize due to physical constraints and the inherent increase in power consumption, development of multiprocessor architectures is becoming the new Holy Grail. In this sense, it is crucial to develop applications that can run on the new multi-core architectures and find out distributions to maximize the potential use of the system. Today most of commercial electronic devices, available in the market, are composed of embedded systems. These devices incorporate recently multi-core processors. Task management onto multiple core/processors is not a trivial issue, and a good task/actor scheduling can yield to significant improvements in terms of efficiency gains and also processor power consumption. Scheduling of data flows between the actors that implement the applications aims to harness multi-core architectures to more types of applications, with an explicit expression of parallelism into the application. On the other hand, the recent development of the MPEG Reconfigurable Video Coding (RVC) standard allows the reconfiguration of the video decoders. RVC is a flexible standard compatible with MPEG developed codecs, making it the ideal tool to integrate into the new multimedia terminals to decode video sequences. With the new versions of the Open RVC-CAL Compiler (Orcc), a static mapping of the actors that implement the functionality of the application can be done once the application executable has been generated. This static mapping must be done for each of the different cores available on the working platform. It has been chosen an embedded system with a processor with two ARMv7 cores. This platform allows us to obtain the desired tests, get as much improvement results from the execution on a single core, and contrast both with a PC-based multiprocessor system. Las posibilidades ofrecidas por el aumento de la velocidad de la frecuencia de reloj de sistemas de un solo procesador est��n siendo agotadas. Las nuevas arquitecturas multiprocesador proporcionan una v��a de desarrollo alternativa en este sentido. El dise��o y optimizaci��n de aplicaciones de descodificaci��n de video que se ejecuten sobre las nuevas arquitecturas permiten un mejor aprovechamiento y favorecen la obtenci��n de mayores rendimientos. Hoy en d��a muchos de los dispositivos comerciales que se est��n lanzando al mercado est��n integrados por sistemas embebidos, que recientemente est��n basados en arquitecturas multin��cleo. El manejo de las tareas de ejecuci��n sobre este tipo de arquitecturas no es una tarea trivial, y una buena planificaci��n de los actores que implementan las funcionalidades puede proporcionar importantes mejoras en t��rminos de eficiencia en el uso de la capacidad de los procesadores y, por ende, del consumo de energ��a. Por otro lado, el reciente desarrollo del est��ndar de Codificaci��n de Video Reconfigurable (RVC), permite la reconfiguraci��n de los descodificadores de video. RVC es un est��ndar flexible y compatible con anteriores codecs desarrollados por MPEG. Esto hace de RVC el est��ndar ideal para ser incorporado en los nuevos terminales multimedia que se est��n comercializando. Con el desarrollo de las nuevas versiones del compilador espec��fico para el desarrollo de lenguaje RVC-CAL (Orcc), en el que se basa MPEG RVC, el mapeo est��tico, para entornos basados en multiprocesador, de los actores que integran un descodificador es posible. Se ha elegido un sistema embebido con un procesador con dos n��cleos ARMv7. Esta plataforma nos permitir�� llevar a cabo las pruebas de verificaci��n y contraste de los conceptos estudiados en este trabajo, en el sentido del desarrollo de descodificadores de video basados en MPEG RVC y del estudio de la planificaci��n y mapeo est��tico de los mismos.

High-level languages for small devices: A case study

In this paper we study, through a concrete case, the feasibility of using a high-level, general-purpose logic language in the design and implementation of applications targeting wearable computers. The case study is a "sound spatializer" which, given real-time sign��is for monaural audio and heading, generates stereo sound which appears to come from a position in space. The use of advanced compile-time transformations and optimizations made it possible to execute code written in a clear style without ef��ciency or architectural concerns on the target device, while meeting strict existing time and memory constraints. The final executable compares favorably with a similar implementation written in C. We believe that this case is representative of a wider class of common pervasive computing applications, and that the techniques we show here can be put to good use in a range of scenarios. This points to the possibility of applying high-level languages, with their associated flexibility, conciseness, ability to be automatically parallelized, sophisticated compile-time tools for analysis and verification, etc., to the embedded systems field without paying an unnecessary performance penalty.

Contribution to the design of waveguide-fed compound-slot arrays by means of equivalent circuit modelling

Los arrays de ranuras son sistemas de antennas conocidos desde los a��os 40, principalmente destinados a formar parte de sistemas r��dar de nav��os de combate y grandes estaciones terrenas donde el tama��o y el peso no eran altamente restrictivos. Con el paso de los a��os y debido sobre todo a importantes avances en materiales y m��todos de fabricaci��n, el rango de aplicaciones de este tipo de sistemas radiantes creci�� en gran medida. Desde nuevas tecnolog��as biom��dicas, sistemas anticolisi��n en autom��viles y navegaci��n en aviones, enlaces de comunicaciones de alta tasa binaria y corta distancia e incluso sistemas embarcados en sat��lites para la transmisi��n de se��al de televisi��n. Dentro de esta familia de antennas, existen dos grupos que destacan por ser los m��s utilizados: las antennas de placas paralelas con las ranuras distribuidas de forma circular o espiral y las agrupaciones de arrays lineales construidos sobre guia de onda. Continuando con las tareas de investigaci��n desarrolladas durante los ��ltimos a��os en el Instituto de Tecnolog��a de Tokyo y en el Grupo de Radiaci��n de la Universidad Polit��cnica de Madrid, la totalidad de esta tesis se centra en este ��ltimo grupo, aunque como se ver�� se separa en gran medida de las t��cnicas de dise��o y metodolog��as convencionales. Los arrays de ranuras rectas y paralelas al eje de la gu��a rectangular que las alimenta son, sin ninguna duda, los modelos m��s empleados debido a la fiabilidad que presentan a altas frecuencias, su capacidad para gestionar grandes cantidades de potencia y la sencillez de su dise��o y fabricaci��n. Sin embargo, tambi��n presentan desventajas como estrecho ancho de banda en p��rdidas de retorno y r��pida degradaci��n del diagrama de radiaci��n con la frecuencia. ��stas son debidas a la naturaleza resonante de sus elementos radiantes: al perder la resonancia, el sistema global se desajusta y sus prestaciones degeneran. En arrays bidimensionales de slots rectos, el campo el��ctrico queda polarizado sobre el plano transversal a las ranuras, correspondi��ndose con el plano de altos l��bulos secundarios. Esta tesis tiene como objetivo el desarrollo de un m��todo sistem��tico de dise��o de arrays de ranuras inclinadas y desplazadas del centro (en lo sucesivo ���ranuras compuestas���), definido en 1971 como uno de los desaf��os a superar dentro del mundo del dise��o de antennas. La t��cnica empleada se basa en el M��todo de los Momentos, la Teor��a de Circuitos y la Teor��a de Conexi��n Aleatoria de Matrices de Dispersi��n. Al tratarse de un m��todo circuital, la primera parte de la tesis se corresponde con el estudio de la aplicabilidad de las redes equivalentes fundamentales, su capacidad para recrear fen��menos f��sicos de la ranura, las limitaciones y ventajas que presentan para caracterizar las diferentes configuraciones de slot compuesto. Se profundiza en las diferencias entre las redes en T y en ! y se condiciona la selecci��n de una u otra dependiendo del tipo de elemento radiante. Una vez seleccionado el tipo de red a emplear en el dise��o del sistema, se ha desarrollado un algoritmo de cascadeo progresivo desde el puerto alimentador hacia el cortocircuito que termina el modelo. Este algoritmo es independiente del n��mero de elementos, la frecuencia central de funcionamiento, del ��ngulo de inclinaci��n de las ranuras y de la red equivalente seleccionada (en T o en !). Se basa en definir el dise��o del array como un Problema de Satisfacci��n de Condiciones (en ingl��s, Constraint Satisfaction Problem) que se resuelve por un m��todo de B��squeda en Retroceso (Backtracking algorithm). Como resultado devuelve un circuito equivalente del array completo adaptado a su entrada y cuyos elementos consumen una potencia acorde a una distribuci��n de amplitud dada para el array. En toda agrupaci��n de antennas, el acoplo mutuo entre elementos a trav��s del campo radiado representa uno de los principales problemas para el ingeniero y sus efectos perjudican a las prestaciones globales del sistema, tanto en adaptaci��n como en capacidad de radiaci��n. El empleo de circuito equivalente se descart�� por la dificultad que supon��a la caracterizaci��n de estos efectos y su inclusi��n en la etapa de dise��o. En esta tesis doctoral el acoplo tambi��n se ha modelado como una red equivalente cuyos elementos son transformadores ideales y admitancias, conectada al conjunto de redes equivalentes que representa el array. Al comparar los resultados estimados en t��rminos de p��rdidas de retorno y radiaci��n con aquellos obtenidos a partir de programas comerciales populares como CST Microwave Studio se confirma la validez del m��todo aqu�� propuesto, el primer m��todo de dise��o sistem��tico de arrays de ranuras compuestos alimentados por gu��a de onda rectangular. Al tratarse de ranuras no resonantes, el ancho de banda en p��rdidas de retorno es mucho mas amplio que el que presentan arrays de slots rectos. Para arrays bidimensionales, el ��ngulo de inclinaci��n puede ajustarse de manera que el campo quede polarizado en los planos de bajos l��bulos secundarios. Adem��s de simulaciones se han dise��ado, construido y medido dos prototipos centrados en la frecuencia de 12GHz, de seis y diez elementos. Las medidas de p��rdidas de retorno y diagrama de radiaci��n revelan excelentes resultados, certificando la bondad del m��todo genuino Method of Moments - Forward Matching Procedure desarrollado a lo largo de esta t��sis. Abstract The slot antenna arrays are well known systems from the decade of 40s, mainly intended to be part of radar systems of large warships and terrestrial stations where size and weight were not highly restrictive. Over the years, mainly due to significant advances in materials and manufacturing methods, the range of applications of this type of radiating systems grew significantly. From new biomedical technologies, collision avoidance systems in cars and aircraft navigation, short communication links with high bit transfer rate and even embedded systems in satellites for television broadcast. Within this family of antennas, two groups stand out as being the most frequent in the literature: parallel plate antennas with slots placed in a circular or spiral distribution and clusters of waveguide linear arrays. To continue the vast research work carried out during the last decades in the Tokyo Institute of Technology and in the Radiation Group at the Universidad Polit��cnica de Madrid, this thesis focuses on the latter group, although it represents a technique that drastically breaks with traditional design methodologies. The arrays of slots straight and parallel to the axis of the feeding rectangular waveguide are without a doubt the most used models because of the reliability that they present at high frequencies, its ability to handle large amounts of power and their simplicity of design and manufacturing. However, there also exist disadvantages as narrow bandwidth in return loss and rapid degradation of the radiation pattern with frequency. These are due to the resonant nature of radiating elements: away from the resonance status, the overall system performance and radiation pattern diminish. For two-dimensional arrays of straight slots, the electric field is polarized transverse to the radiators, corresponding to the plane of high side-lobe level. This thesis aims to develop a systematic method of designing arrays of angled and displaced slots (hereinafter "compound slots"), defined in 1971 as one of the challenges to overcome in the world of antenna design. The used technique is based on the Method of Moments, Circuit Theory and the Theory of Scattering Matrices Connection. Being a circuitry-based method, the first part of this dissertation corresponds to the study of the applicability of the basic equivalent networks, their ability to recreate the slot physical phenomena, their limitations and advantages presented to characterize different compound slot configurations. It delves into the differences of T and ! and determines the selection of the most suitable one depending on the type of radiating element. Once the type of network to be used in the system design is selected, a progressive algorithm called Forward Matching Procedure has been developed to connect the proper equivalent networks from the feeder port to shorted ending. This algorithm is independent of the number of elements, the central operating frequency, the angle of inclination of the slots and selected equivalent network (T or ! networks). It is based on the definition of the array design as a Constraint Satisfaction Problem, solved by means of a Backtracking Algorithm. As a result, the method returns an equivalent circuit of the whole array which is matched at its input port and whose elements consume a power according to a given amplitude distribution for the array. In any group of antennas, the mutual coupling between elements through the radiated field represents one of the biggest problems that the engineer faces and its effects are detrimental to the overall performance of the system, both in radiation capabilities and return loss. The employment of an equivalent circuit for the array design was discarded by some authors because of the difficulty involved in the characterization of the coupling effects and their inclusion in the design stage. In this thesis the coupling has also been modeled as an equivalent network whose elements are ideal transformers and admittances connected to the set of equivalent networks that represent the antennas of the array. By comparing the estimated results in terms of return loss and radiation with those obtained from popular commercial software as CST Microwave Studio, the validity of the proposed method is fully confirmed, representing the first method of systematic design of compound-slot arrays fed by rectangular waveguide. Since these slots do not work under the resonant status, the bandwidth in return loss is much wider than the longitudinal-slot arrays. For the case of two-dimensional arrays, the angle of inclination can be adjusted so that the field is polarized at the low side-lobe level plane. Besides the performed full-wave simulations two prototypes of six and ten elements for the X-band have been designed, built and measured, revealing excellent results and agreement with the expected results. These facts certify that the genuine technique Method of Moments - Matching Forward Procedure developed along this thesis is valid and trustable.

Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling

Adaptive embedded systems are required in various applications. This work addresses these needs in the area of adaptive image compression in FPGA devices. A simplified version of an evolution strategy is utilized to optimize wavelet filters of a Discrete Wavelet Transform algorithm. We propose an adaptive image compression system in FPGA where optimized memory architecture, parallel processing and optimized task scheduling allow reducing the time of evolution. The proposed solution has been extensively evaluated in terms of the quality of compression as well as the processing time. The proposed architecture reduces the time of evolution by 44% compared to our previous reports while maintaining the quality of compression unchanged with respect to existing implementations. The system is able to find an optimized set of wavelet filters in less than 2 min whenever the input type of data changes.

Design of a remote controlled hovercraft

Este informe trata el dise��o, desarrollo y construcci��n de un aerodeslizador de peque��o tama��o, equipado con control remoto que permite al usuario actuar sobre la velocidad y direcci��n del mismo. Este proyecto podr�� ser utilizado en un futuro como base para el desarrollo de aplicaciones m��s complejas. Un aerodeslizador es un medio de transporte cuyo chasis se eleva sobre el suelo por medio de un motor impulsor que hincha una falda colocada en la parte inferior del mismo. Adem��s, uno o m��s motores se colocan en la parte trasera del veh��culo para propulsarlo. El hecho de que el aerodeslizador no este en contacto directo con la tierra, hace que pueda moverse tanto por tierra como sobre el agua o hielo y que sea capaz de superar peque��os obst��culos. Por otra parte, este hecho se convierte a su vez en un problema debido a que su fuerza de rozamiento al desplazarse es muy peque��a, lo que provoca que sea muy dif��cil de frenar, y tienda a girar por s�� mismo debido a la inercia del movimiento y a las fuerzas provocadas por las corrientes de aire debajo del chasis. Sin embargo, para este proyecto no se ha colocado una falda debajo del mismo, debido a que su dise��o es bastante complicado, por lo tanto la fricci��n con el suelo es menor, aumentando los problemas detallados con anterioridad. El proyecto consta de dos partes, mando a distancia y aerodeslizador, que se conectan a trav��s de antenas de radiofrecuencia (RF). El dise��o y desarrollo de cada una ha sido realizado de manera separada exceptuando la parte de las comunicaciones entre ambas. El mando a distancia se divide en tres partes. La primera est�� compuesta por la interfaz de usuario y el circuito que genera las se��ales anal��gicas correspondientes a sus indicaciones. La interfaz de usuario la conforman tres potenci��metros: uno rotatorio y dos deslizantes. El rotatorio se utiliza para controlar la direcci��n de giro del aerodeslizador, mientras que cada uno de los deslizantes se emplea para controlar la fuerza del motor impulsor y del propulsor respectivamente. En los tres casos los potenci��metros se colocan en el circuito de manera que act��an como divisores de tensi��n controlables. La segunda parte se compone de un microcontrolador de la familia PSoC. Esta familia de microcontroladores se caracteriza por tener una gran adaptabilidad a la aplicaci��n en la que se quieran utilizar debido a la posibilidad de elecci��n de los perif��ricos, tanto anal��gicos como digitales, que forman parte del microcontrolador. Para el mando a distancia se configura con tres conversores A/D que se encargan de transformar las se��ales procedentes de los potenci��metros, tres amplificadores programables para trabajar con toda la escala de los conversores, un LCD que se utiliza para depurar el c��digo en C con el que se programa y un m��dulo SPI que es la interfaz que conecta el microcontrolador con la antena. Adem��s, se utilizan cuatro pines externos para elegir el canal de transmisi��n de la antena. La tercera parte es el m��dulo transceptor de radio frecuencia (RF) QFM-TRX1-24G, que en el mando a distancia funciona como transmisor. ��ste utiliza codificaci��n Manchester para asegurar bajas tasas de error. Como alimentaci��n para los circuitos del mando a distancia se utilizan cuatro pilas AA de 1,5 voltios en serie. En el aerodeslizador se pueden distinguir cinco partes. La primera es el m��dulo de comunicaciones, que utiliza el mismo transceptor que en el mando a distancia, pero esta vez funciona como receptor y por lo tanto servir�� como entrada de datos al sistema haciendo llegar las instrucciones del usuario. Este m��dulo se comunica con el siguiente, un microcontrolador de la familia PSoC, a trav��s de una interfaz SPI. En este caso el microcontrolador se configura con: un modulo SPI, un LCD utilizado para depurar el c��digo y tres m��dulos PWM (2 de 8 bits y uno de 16 bits) para controlar los motores y el servo del aerodeslizador. Adem��s, se utilizan cuatro pines externos para seleccionar el canal de recepci��n de datos. La tercera y cuarta parte se pueden considerar conjuntamente. Ambas est��n compuestas por el mismo circuito electr��nico basado en transistores MOSFET. A la puerta de cada uno de los transistores llega una se��al PWM de 100 kilohercios que proviene del microcontrolador, que se encarga de controlar el modo de funcionamiento de los transistores, que llevan acoplado un disipador de calor para evitar que se quemen. A su vez, los transistores hacen funcionar al dos ventiladores, que act��an como motores, el impulsor y el propulsor del aerodeslizador. La quinta y ��ltima parte es un servo est��ndar para modelismo. El servo est�� controlado por una se��al PWM, en la que la longitud del pulso positivo establece la posici��n de la cabeza del servo, girando en uno u otra direcci��n seg��n las instrucciones enviadas desde el mando a distancia por el usuario. Para el aerodeslizador se han utilizado dos fuentes de alimentaci��n diferentes: una compuesta por 4 pilas AA de 1,5 voltios en serie que alimentar��n al microcontrolador y al servo, y 4 bater��as de litio recargables de 3,2 voltios en serie que alimentan el circuito de los motores. La ��ltima parte del proyecto es el montaje y ensamblaje final de los dispositivos. Para el chasis del aerodeslizador se ha utilizado una cubierta rectangular de poli-estireno expandido, habitualmente encontrado en el embalaje de productos fr��giles. Este material es bastante ligero y con una alta resistencia a los golpes, por lo que es ideal para el prop��sito del proyecto. En el chasis se han realizado dos agujeros: uno circular situado en el centro del mismo en el se introduce y se ajusta con pegamento el motor impulsor, y un agujero con la forma del servo, situado en uno del los laterales estrechos del rect��ngulo, en el que se acopla el mismo. El motor propulsor est�� adherido al cabezal giratorio del servo de manera que rota a la vez que ��l, haciendo girar al aerodeslizador. El resto de circuitos electr��nicos y las bater��as se fijan al chasis mediante cinta adhesiva y pegamento procurando en todo momento repartir el peso de manera homog��nea por todo el chasis para aumentar la estabilidad del aerodeslizador. SUMMARY: In this final year project a remote controlled hovercraft was designed using mainly technology that is well known by students in the embedded systems programme. This platform could be used to develop further and more complex projects. The system was developed dividing the work into two parts: remote control and hovercraft. The hardware was of the hovercraft and the remote control was designed separately; however, the software was designed at the same time since it was needed to develop the communication system. The result of the project was a remote control hovercraft which has a user friendly interface. The system was designed based on microprocessor technologies and uses common remote control technologies. The system has been designed with technology commonly used by the students in Metropolia University so that it can be readily understood in order to develop other projects based on this platform.

Portado del algoritmo de Viterbi a una arquitectura multiprocesador

Cada vez es m��s frecuente que los sistemas de comunicaciones realicen buena parte de sus funciones (modulaci��n y demodulaci��n, codificaci��n y decodificaci��n...) mediante software en lugar de utilizar hardware dedicado. Esta t��cnica se denomina ���Radio software���. El objetivo de este PFC es estudiar un algoritmo implementado en C empleado en sistemas de comunicaciones modernos, en concreto la decodificaci��n de Viterbi, el cual se encarga de corregir los posibles errores producidos a lo largo de la comunicaci��n, para poder trasladarlo a sistemas empotrados multiprocesador. Partiendo de un c��digo en C para el decodificador que realiza todas sus operaciones en serie, en este Proyecto fin de carrera se ha paralelizado dicho c��digo, es decir, que el trabajo que realizaba un solo hilo para el caso del c��digo serie, es procesado por un n��mero de hilos configurables por el usuario, persiguiendo que el tiempo de ejecuci��n se reduzca, es decir, que el programa paralelizado se ejecute de una manera m��s r��pida. El trabajo se ha realizado en un PC con sistema operativo Linux, pero la versi��n paralelizada del c��digo puede ser empleada en un sistema empotrado multiprocesador en el cual cada procesador ejecuta el c��digo correspondiente a uno de los hilos de la versi��n de PC. ABSTRACT It is increasingly common for communications systems to perform most of its functions (modulation and demodulation, coding and decoding) by software instead of than using dedicated hardware. This technique is called: ���Software Radio���. The aim of the PFC is to study an implemented algorithm in C language used in modern communications systems, particularly Viterbi decoding, which amends any possible error produced during the communication, in order to be able to move multiprocessor embedded systems. Starting from a C code of the decoder that performs every single operation in serial, in this final project, this code has been parallelized, which means that the work used to be done by just a single thread in the case of serial code, is processed by a number of threads configured by the user, in order to decrease the execution time, meaning that the parallelized program is executed faster. The work has been carried out on a PC using Linux operating system, but the parallelized version of the code could also be used in an embedded multiprocessor system in which each processor executes the corresponding code to every single one of the threads of the PC version.

Methodologies for implement video decoders over multiprocessor platforms

The latest video coding standards developed, like HEVC (High Efficiency Video Coding, approved in January 2013), require for their implementation the use of devices able to support a high computational load. Considering that currently it is not enough the usage of one unique Digital Signal Processor (DSP), multicore devices have appeared recently in the market. However, due to its novelty, the working methodology that allows produce solutions for these configurations is in a very initial state, since currently the most part of the work needs to be performed manually. In consequence, the objective set consists on finding methodologies that ease this process. The study has been focused on extend a methodology, under development, for the generation of solutions for PCs and embedded systems. During this study, the standards RVC (Reconfigurable Video Coding) and HEVC have been employed, as well as DSPs of the Texas Instruments company. In its development, it has been tried to address all the factors that influence both the development and deployment of these new implementations of video decoders, ranging from tools up to aspects of the partitioning of algorithms, without this can cause a drop in application performance. The results of this study are the description of the employed methodology, the characterization of the software migration process and performance measurements for the HEVC standard in an RVC-based implementation. RESUMEN Los est��ndares de codificaci��n de v��deo desarrollados m��s recientemente, como HEVC (High Efficiency Video Coding, aprobado en enero de 2013), requieren para su implementaci��n el uso de dispositivos capaces de soportar una elevada carga computacional. Teniendo en cuenta que actualmente no es suficiente con utilizar un ��nico Procesador Digital de Se��al (DSP), han aparecido recientemente dispositivos multin��cleo en el mercado. Sin embargo, debido a su novedad, la metodolog��a de trabajo que permite elaborar soluciones para tales configuraciones se encuentra en un estado muy inicial, ya que actualmente la mayor parte del trabajo debe realizarse manualmente. En consecuencia, el objetivo marcado consiste en encontrar metodolog��as que faciliten este proceso. El estudio se ha centrado en extender una metodolog��a, en desarrollo, para la generaci��n de soluciones para PC y sistemas empotrados. Durante dicho estudio se han empleado los est��ndares RVC (Reconfigurable Video Coding) y HEVC, as�� como DSPs de la compa����a Texas Instruments. En su desarrollo se ha tratado de atender a todos los factores que influyen tanto en el desarrollo como en la puesta en marcha de estas nuevas implementaciones de descodificadores de v��deo; abarcando desde las herramientas a utilizar hasta aspectos del particionado de los algoritmos, sin que por ello se produzca una reducci��n en el rendimiento de las aplicaciones. Los resultados de este estudio son una descripci��n de la metodolog��a empleada, la caracterizaci��n del proceso de migraci��n de software, y medidas de rendimiento para el est��ndar HEVC en una implementaci��n basada en RVC.

Radio propagation modeling and measurements for ZigBee based indoor wireless sensor networks

The deployment of nodes in Wireless Sensor Networks (WSNs) arises as one of the biggest challenges of this field, which involves in distributing a large number of embedded systems to fulfill a specific application. The connectivity of WSNs is difficult to estimate due to the irregularity of the physical environment and affects the WSN designers? decision on deploying sensor nodes. Therefore, in this paper, a new method is proposed to enhance the efficiency and accuracy on ZigBee propagation simulation in indoor environments. The method consists of two steps: automatic 3D indoor reconstruction and 3D ray-tracing based radio simulation. The automatic 3D indoor reconstruction employs unattended image classification algorithm and image vectorization algorithm to build the environment database accurately, which also significantly reduces time and efforts spent on non-radio propagation issue. The 3D ray tracing is developed by using kd-tree space division algorithm and a modified polar sweep algorithm, which accelerates the searching of rays over the entire space. Signal propagation model is proposed for the ray tracing engine by considering both the materials of obstacles and the impact of positions along the ray path of radio. Three different WSN deployments are realized in the indoor environment of an office and the results are verified to be accurate. Experimental results also indicate that the proposed method is efficient in pre-simulation strategy and 3D ray searching scheme and is suitable for different indoor environments.