Biochemical, single-channel, whole-cell patch clamp, and pharmacological analyses of endogenous TRPM4 channels in HEK293 cells

Human embryonic kidney cells 293 (HEK293) are widely used as cellular heterologous expression systems to study transfected ion channels. This work characterizes the endogenous expression of TRPM4 channels in HEK293 cells. TRPM4 is an intracellular Ca(2+)-activated non-selective cationic channel expressed in many cell types. Western blot analyses have revealed the endogenous expression of TRPM4. Single channel 22pS conductance with a linear current-voltage relationship was observed using the inside-out patch clamp configuration in the presence of intracellular Ca(2+). The channels were permeable to the monovalent cations Na(+) and K(+), but not to Ca(2+). The open probability was voltage-dependent, being higher at positive potentials. Using the whole-cell patch clamp "ruptured patch" configuration, the amplitude of the intracellular Ca(2+)-activated macroscopic current was dependent on time after patch rupture. Initial transient activation followed by a steady-increase reaching a plateau phase was observed. Biophysical analyses of the macroscopic current showed common properties with those from HEK293 cells stably transfected with human TRPM4b, with the exception of current time course and Ca(2+) sensitivity. The endogenous macroscopic current reached the plateau faster and required 61.9±3.5μM Ca(2+) to be half-maximally activated versus 84.2±1.5μM for the transfected current. The pharmacological properties, however, were similar in both conditions. One hundred μM of flufenamic acid and 9-phenanthrol strongly inhibited the endogenous current. Altogether, the data demonstrate the expression of endogenous TRMP4 channels in HEK293 cells. This observation should be taken into account when using this cell line to study TRPM4 or other types of Ca(2+)-activated channels.

Acute effects of stochastic resonance whole body vibration

AIM: To investigate the acute effects of stochastic resonance whole body vibration (SR-WBV) training to identify possible explanations for preventive effects against musculoskeletal disorders. METHODS: Twenty-three healthy, female students participated in this quasi-experimental pilot study. Acute physiological and psychological effects of SR-WBV training were examined using electromyography of descending trapezius (TD) muscle, heart rate variability (HRV), different skin parameters (temperature, redness and blood flow) and self-report questionnaires. All subjects conducted a sham SR-WBV training at a low intensity (2 Hz with noise level 0) and a verum SR-WBV training at a higher intensity (6 Hz with noise level 4). They were tested before, during and after the training. Conclusions were drawn on the basis of analysis of variance. RESULTS: Twenty-three healthy, female students participated in this study (age = 22.4 ± 2.1 years; body mass index = 21.6 ± 2.2 kg/m2). Muscular activity of the TD and energy expenditure rose during verum SR-WBV compared to baseline and sham SR-WBV (all P < 0.05). Muscular relaxation after verum SR-WBV was higher than at baseline and after sham SR-WBV (all P < 0.05). During verum SR-WBV the levels of HRV were similar to those observed during sham SR-WBV. The same applies for most of the skin characteristics, while microcirculation of the skin of the middle back was higher during verum compared to sham SR-WBV (P < 0.001). Skin redness showed significant changes over the three measurement points only in the middle back area (P = 0.022). There was a significant rise from baseline to verum SR-WBV (0.86 ± 0.25 perfusion units; P = 0.008). The self-reported chronic pain grade indicators of pain, stiffness, well-being, and muscle relaxation showed a mixed pattern across conditions. Muscle and joint stiffness (P = 0.018) and muscular relaxation did significantly change from baseline to different conditions of SR-WBV (P < 0.001). Moreover, muscle relaxation after verum SR-WBV was higher than after sham SR-WBV (P < 0.05). CONCLUSION: Verum SR-WBV stimulated musculoskeletal activity in young healthy individuals while cardiovascular activation was low. Training of musculoskeletal capacity and immediate increase in musculoskeletal relaxation are potential mediators of pain reduction in preventive trials.

Governance and the Capacity to Manage Resilience in Regional Social-Ecological Systems

The sustainability of regional development can be usefully explored through several different lenses. In situations in which uncertainties and change are key features of the ecological landscape and social organization, critical factors for sustainability are resilience, the capacity to cope and adapt, and the conservation of sources of innovation and renewal. However, interventions in social-ecological systems with the aim of altering resilience immediately confront issues of governance. Who decides what should be made resilient to what? For whom is resilience to be managed, and for what purpose? In this paper we draw on the insights from a diverse set of case studies from around the world in which members of the Resilience Alliance have observed or engaged with sustainability problems at regional scales. Our central question is: How do certain attributes of governance function in society to enhance the capacity to manage resilience? Three specific propositions were explored: ( 1) participation builds trust, and deliberation leads to the shared understanding needed to mobilize and self-organize; ( 2) polycentric and multilayered institutions improve the fit between knowledge, action, and social-ecological contexts in ways that allow societies to respond more adaptively at appropriate levels; and ( 3) accountable authorities that also pursue just distributions of benefits and involuntary risks enhance the adaptive capacity of vulnerable groups and society as a whole. Some support was found for parts of all three propositions. In exploring the sustainability of regional social-ecological systems, we are usually faced with a set of ecosystem goods and services that interact with a collection of users with different technologies, interests, and levels of power. In this situation in our roles as analysts, facilitators, change agents, or stakeholders, we not only need to ask: The resilience of what, to what? We must also ask: For whom?

Heavy Metals in Crop Plants: Transport and Redistribution Processes on the Whole Plant Level

Copper, zinc, manganese, iron, nickel and molybdenum are essential micronutrients for plants. However, when present in excess they may damage the plant or decrease the quality of harvested plant products. Some other heavy metals such as cadmium, lead or mercury are not needed by plants and represent pollutants. The uptake into the roots, the loading into the xylem, the acropetal transport to the shoot with the transpiration stream and the further redistribution in the phloem are crucial for the distribution in aerial plant parts. This review is focused on long-distance transport of heavy metals via xylem and phloem and on interactions between the two transport systems. Phloem transport is the basis for the redistribution within the shoot and for the accumulation in fruits and seeds. Solutes may be transferred from the xylem to the phloem (e.g., in the small bundles in stems of cereals, in minor leaf veins). Nickel is highly phloem-mobile and directed to expanding plant parts. Zinc and to a lesser degree also cadmium are also mobile in the phloem and accumulate in meristems (root tips, shoot apex, axillary buds). Iron and manganese are characterized by poor phloem mobility and are retained in older leaves.

Governance and the Capacity to Manage Resilience in Regional Social-Ecological Systems

The sustainability of regional development can be usefully explored through several different lenses. In situations in which uncertainties and change are key features of the ecological landscape and social organization, critical factors for sustainability are resilience, the capacity to cope and adapt, and the conservation of sources of innovation and renewal. However, interventions in social-ecological systems with the aim of altering resilience immediately confront issues of governance. Who decides what should be made resilient to what? For whom is resilience to be managed, and for what purpose? In this paper we draw on the insights from a diverse set of case studies from around the world in which members of the Resilience Alliance have observed or engaged with sustainability problems at regional scales. Our central question is: How do certain attributes of governance function in society to enhance the capacity to manage resilience? Three specific propositions were explored: ( 1) participation builds trust, and deliberation leads to the shared understanding needed to mobilize and self-organize; ( 2) polycentric and multilayered institutions improve the fit between knowledge, action, and social-ecological contexts in ways that allow societies to respond more adaptively at appropriate levels; and ( 3) accountable authorities that also pursue just distributions of benefits and involuntary risks enhance the adaptive capacity of vulnerable groups and society as a whole. Some support was found for parts of all three propositions. In exploring the sustainability of regional social-ecological systems, we are usually faced with a set of ecosystem goods and services that interact with a collection of users with different technologies, interests, and levels of power. In this situation in our roles as analysts, facilitators, change agents, or stakeholders, we not only need to ask: The resilience of what, to what? We must also ask: For whom?

Review of the Performance of Residential PV systems in Belgium

The main objective of this paper is to review the state of the art of residential PV systems in Belgium by the analysis of the operational data of 993 installations. For that, three main questions are posed: how much energy do they produce? What level of performance is associated to their production? Which are the key parameters that most influence their quality? This work brings answers to these questions. A middling commercial PV system, optimally oriented, produces a mean annual energy of 892 kWh/kWp. As a whole, the orientation of PV generators causes energy productions to be some 6% inferior to optimally oriented PV systems. The mean performance ratio is 78% and the mean performance index is 85%. That is to say, the energy produced by a typical PV system in Belgium is 15% inferior to the energy produced by a very high quality PV system. Finally, on average, the real power of the PV modules falls 5% below its corresponding nominal power announced on the manufacturer's datasheet. Differences between real and nominal power of up to 16% have been detected.

Review of the Performance of Residential PV systems in France

The main objective of this paper is to review the state of the art of residential PV systems in France. This is done analyzing the operational data of 6868 installations. Three main questions are posed. How much energy do they produce? What level of performance is associated to their production? Which are the key parameters that most influence their quality? During the year 2010, the PV systems in France have produced a mean annual energy of 1163 kWh/kWp. As a whole, the orientation of PV generators causes energy productions to be some 7% inferior to optimally oriented PV systems. The mean Performance Ratio is 76% and the mean Performance Index is 85%. That is to say, the energy produced by a typical PV system in France is 15% inferior to the energy produced by a very high quality PV system. On average, the real power of the PV modules falls 4.9% below its corresponding nominal power announced on the manufacturer's datasheet. A brief analysis by PV modules technology has led to relevant observations about two technologies in particular. On the one hand, the PV systems equipped with heterojunction with intrinsic thin layer (HIT) modules show performances higher than average. On the other hand, the systems equipped with the copper indium (di)selenide (CIS) modules show a real power that is 16% lower than their nominal value.

Performance Analysis of 10,000 Residential PV Systems in France and Belgium

The main objective of this paper is to review the state of the art of residential PV systems in France and Belgium. This is done analyzing the operational data of 10650 PV systems (9657 located in France and 993 in Belgium). Three main questions are posed. How much energy do they produce? What level of performance is associated to their production? Which are the key parameters that most influence their quality? During the year 2010, the PV systems in France have produced a mean annual energy of 1163 kWh/kWp in France and 852 kWh/kWp in Belgium. As a whole, the orientation of PV generators causes energy productions to be some 7% inferior to optimally oriented PV systems. The mean Performance Ratio is 76% in France and 78% in Belgium, and the mean Performance Index is 85% in both countries. On average, the real power of the PV modules falls 4.9% below its corresponding nominal power announced on the manufacturer?s datasheet. A brief analysis by PV modules technology has lead to relevant observations about two technologies in particular. On the one hand, the PV systems equipped with Heterojunction with Intrinsic. Thin layer (HIT) modules show performances higher than average. On the other hand, the systems equipped with Copper Indium (di)Selenide (CIS) modules show a real power that is 16 % lower than their nominal value.

Resilience analysis of networked systems-of-systems based on structural and dynamic interdependencies

Critical infrastructures support everyday activities in modern societies, facilitating the exchange of services and quantities of various nature. Their functioning is the result of the integration of diverse technologies, systems and organizations into a complex network of interconnections. Benefits from networking are accompanied by new threats and risks. In particular, because of the increased interdependency, disturbances and failures may propagate and render unstable the whole infrastructure network. This paper presents a methodology of resilience analysis of networked systems of systems. Resilience generalizes the concept of stability of a system around a state of equilibrium, with respect to a disturbance and its ability of preventing, resisting and recovery. The methodology provides a tool for the analysis of off-equilibrium conditions that may occur in a single system and propagate through the network of dependencies. The analysis is conducted in two stages. The first stage of the analysis is qualitative. It identifies the resilience scenarios, i.e. the sequence of events, triggered by an initial disturbance, which include failures and the system response. The second stage is quantitative. The most critical scenarios can be simulated, for the desired parameter settings, in order to check if they are successfully handled, i.e recovered to nominal conditions, or they end into the network failure. The proposed methodology aims at providing an effective support to resilience-informed design.

Choked flow in water/CO2 solutions on air-independent propulsion systems

We develop a simplified model of choked flow in pipes for CO2-water solutions as an important step in the modelling of a whole hydraulic system with the intention of eliminating the carbon dioxide generated in air-independent submarine propulsion. The model is based on an approximate fitting of the homogeneous isentropic solution upstream of a valve (or any other area restriction), for given fluid conditions at the entrance. The relative maximum choking back-pressure is computed as a function of area restriction ratio. Although the procedure is generic for gas solutions, numeric values for the non-dimensional parameters in the analysis are developed only for choking in the case of carbon dioxide solutions up to the pure-water limit.

solaR: Solar Radiation and Photovoltaic Systems with R

The solaR package allows for reproducible research both for photovoltaics (PV) systems performance and solar radiation. It includes a set of classes, methods and functions to calculate the sun geometry and the solar radiation incident on a photovoltaic generator and to simulate the performance of several applications of the photovoltaic energy. This package performs the whole calculation procedure from both daily and intradaily global horizontal irradiation to the final productivity of grid-connected PV systems and water pumping PV systems. It is designed using a set of S4 classes whose core is a group of slots with multivariate time series. The classes share a variety of methods to access the information and several visualization methods. In addition, the package provides a tool for the visual statistical analysis of the performance of a large PV plant composed of several systems. Although solaR is primarily designed for time series associated to a location defined by its latitude/longitude values and the temperature and irradiation conditions, it can be easily combined with spatial packages for space-time analysis.

Reliability and quality in the area of statistical thinking in Engineering

There is remarkable growing concern about the quality control at the time, which has led to the search for methods capable of addressing effectively the reliability analysis as part of the Statistic. Managers, researchers and Engineers must understand that 'statistical thinking' is not just a set of statistical tools. They should start considering 'statistical thinking' from a 'system', which means, developing systems that meet specific statistical tools and other methodologies for an activity. The aim of this article is to encourage them (engineers, researchers and managers) to develop a new way of thinking.

Contribution to proactivity in mobile context-aware recommender systems

Los sistemas de recomendación son potentes herramientas de filtrado de información que permiten a usuarios solicitar sugerencias sobre ítems que cubran sus necesidades. Tradicionalmente estas recomendaciones han estado basadas en opiniones de los mismos, así como en datos obtenidos de su consumo histórico o comportamiento en el propio sistema. Sin embargo, debido a la gran penetración y uso de los dispositivos móviles en nuestra sociedad, han surgido nuevas oportunidades en el campo de los sistemas de recomendación móviles gracias a la información contextual que se puede obtener sobre la localización o actividad de los usuarios. Debido a este estilo de vida en el que todo tiende a la movilidad y donde los usuarios están plenamente interconectados, la información contextual no sólo es física, sino que también adquiere una dimensión social. Todo esto ha dado lugar a una nueva área de investigación relacionada con los Sistemas de Recomendación Basados en Contexto (CARS) móviles donde se busca incrementar el nivel de personalización de las recomendaciones al usar dicha información. Por otro lado, este nuevo escenario en el que los usuarios llevan en todo momento un terminal móvil consigo abre la puerta a nuevas formas de recomendar. Sustituir el tradicional patrón de uso basado en petición-respuesta para evolucionar hacia un sistema proactivo es ahora posible. Estos sistemas deben identificar el momento más adecuado para generar una recomendación sin una petición explícita del usuario, siendo para ello necesario analizar su contexto. Esta tesis doctoral propone un conjunto de modelos, algoritmos y métodos orientados a incorporar proactividad en CARS móviles, a la vez que se estudia el impacto que este tipo de recomendaciones tienen en la experiencia de usuario con el fin de extraer importantes conclusiones sobre "qué", "cuándo" y "cómo" se debe notificar proactivamente. Con este propósito, se comienza planteando una arquitectura general para construir CARS móviles en escenarios sociales. Adicionalmente, se propone una nueva forma de representar el proceso de recomendación a través de una interfaz REST, lo que permite crear una arquitectura independiente de dispositivo y plataforma. Los detalles de su implementación tras su puesta en marcha en el entorno bancario español permiten asimismo validar el sistema construido. Tras esto se presenta un novedoso modelo para incorporar proactividad en CARS móviles. Éste muestra las ideas principales que permiten analizar una situación para decidir cuándo es apropiada una recomendación proactiva. Para ello se presentan algoritmos que establecen relaciones entre lo propicia que es una situación y cómo esto influye en los elementos a recomendar. Asimismo, para demostrar la viabilidad de este modelo se describe su aplicación a un escenario de recomendación para herramientas de creación de contenidos educativos. Siguiendo el modelo anterior, se presenta el diseño e implementación de nuevos interfaces móviles de usuario para recomendaciones proactivas, así como los resultados de su evaluación entre usuarios, lo que aportó importantes conclusiones para identificar cuáles son los factores más relevantes a considerar en el diseño de sistemas proactivos. A raíz de los resultados anteriores, el último punto de esta tesis presenta una metodología para calcular cuán apropiada es una situación de cara a recomendar de manera proactiva siguiendo el modelo propuesto. Como conclusión, se describe la validación llevada a cabo tras la aplicación de la arquitectura, modelo de recomendación y métodos descritos en este trabajo en una red social de aprendizaje europea. Finalmente, esta tesis discute las conclusiones obtenidas a lo largo de la extensa investigación llevada a cabo, y que ha propiciado la consecución de una buena base teórica y práctica para la creación de sistemas de recomendación móviles proactivos basados en información contextual. ABSTRACT Recommender systems are powerful information filtering tools which offer users personalized suggestions about items whose aim is to satisfy their needs. Traditionally the information used to make recommendations has been based on users’ ratings or data on the item’s consumption history and transactions carried out in the system. However, due to the remarkable growth in mobile devices in our society, new opportunities have arisen to improve these systems by implementing them in ubiquitous environments which provide rich context-awareness information on their location or current activity. Because of this current all-mobile lifestyle, users are socially connected permanently, which allows their context to be enhanced not only with physical information, but also with a social dimension. As a result of these novel contextual data sources, the advent of mobile Context-Aware Recommender Systems (CARS) as a research area has appeared to improve the level of personalization in recommendation. On the other hand, this new scenario in which users have their mobile devices with them all the time offers the possibility of looking into new ways of making recommendations. Evolving the traditional user request-response pattern to a proactive approach is now possible as a result of this rich contextual scenario. Thus, the key idea is that recommendations are made to the user when the current situation is appropriate, attending to the available contextual information without an explicit user request being necessary. This dissertation proposes a set of models, algorithms and methods to incorporate proactivity into mobile CARS, while the impact of proactivity is studied in terms of user experience to extract significant outcomes as to "what", "when" and "how" proactive recommendations have to be notified to users. To this end, the development of this dissertation starts from the proposal of a general architecture for building mobile CARS in scenarios with rich social data along with a new way of managing a recommendation process through a REST interface to make this architecture multi-device and cross-platform compatible. Details as regards its implementation and evaluation in a Spanish banking scenario are provided to validate its usefulness and user acceptance. After that, a novel model is presented for proactivity in mobile CARS which shows the key ideas related to decide when a situation warrants a proactive recommendation by establishing algorithms that represent the relationship between the appropriateness of a situation and the suitability of the candidate items to be recommended. A validation of these ideas in the area of e-learning authoring tools is also presented. Following the previous model, this dissertation presents the design and implementation of new mobile user interfaces for proactive notifications. The results of an evaluation among users testing these novel interfaces is also shown to study the impact of proactivity in the user experience of mobile CARS, while significant factors associated to proactivity are also identified. The last stage of this dissertation merges the previous outcomes to design a new methodology to calculate the appropriateness of a situation so as to incorporate proactivity into mobile CARS. Additionally, this work provides details about its validation in a European e-learning social network in which the whole architecture and proactive recommendation model together with its methods have been implemented. Finally, this dissertation opens up a discussion about the conclusions obtained throughout this research, resulting in useful information from the different design and implementation stages of proactive mobile CARS.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

Quality assurance systems in the production and marketing of fresh peaches.

Due to the fast rate of peach post-harvest ripening, damage due to mechanical handling, externally appreciated as bruises and soft areas, is a real problem that leads to an early harvesting and poor quality of the fruits, as perceived by the consumers. More and more, the European consumer asks for good taste and freshness of fruits and vegetables, and these quality factors are not included in standards, nor in most of the producers' practices. Fruit processing and marketing centres (co-operatives) are increasingly interested in adopting quality controls in their processes. ISO 9000 procedures are being applied in some food areas, primarily milk and meat processors, but no generalised procedures have been developed until the present time to be applied to fresh product processes. All different peach and nectarine varieties that are harvested and handled in Murcia cooperatives and sold in a large supermarket in Madrid were analysed during the whole 1997 season (early May to late August). A total number of 78 samples of 25 fruits (co-operative) or 10 fruits (market), were tested in the laboratory for mechanical, optical, chemical and tasting quality. The variability and relationships between all these quality parameters are presented and discussed, and sampling unit sizes which would be advisable for quality control are calculated.