Cryogenic on-chip multiplexer for the study of quantum transport in 256 split-gate devices

We present a multiplexing scheme for the measurement of large numbers of mesoscopic devices in cryogenic systems. The multiplexer is used to contact an array of 256 split gates on a GaAs/AlGaAs heterostructure, in which each split gate can be measured individually. The low-temperature conductance of split-gate devices is governed by quantum mechanics, leading to the appearance of conductance plateaux at intervals of 2e^2/h. A fabrication-limited yield of 94% is achieved for the array, and a "quantum yield" is also defined, to account for disorder affecting the quantum behaviour of the devices. The quantum yield rose from 55% to 86% after illuminating the sample, explained by the corresponding increase in carrier density and mobility of the two-dimensional electron gas. The multiplexer is a scalable architecture, and can be extended to other forms of mesoscopic devices. It overcomes previous limits on the number of devices that can be fabricated on a single chip due to the number of electrical contacts available, without the need to alter existing experimental set ups.

Gate commutated thyristor with voltage independent maximum controllable current

In this letter, we use a novel 3-D model, earlier calibrated with experimental results on standard gate commutated thyristors (GCTs), with the aim to explain the physics behind the high-power technology (HPT) GCT, to investigate what impact this design would have on 24 mm diameter GCTs, and to clarify the mechanisms that limit safe switching at different dc-link voltages. The 3-D simulation results show that the HPT design can increase the maximum controllable current in 24 mm diameter devices beyond the realm of GCT switching, known as the hard-drive limit. It is proposed that the maximum controllable current becomes independent of the dc-link voltage for the complete range of operating voltage. © 1980-2012 IEEE.

Electron-beam patterning of polymer electrolyte films to make multiple nanoscale gates for nanowire transistors

We report an electron-beam based method for the nanoscale patterning of the poly(ethylene oxide)/LiClO4 polymer electrolyte. We use the patterned polymer electrolyte as a high capacitance gate dielectric in single nanowire transistors and obtain subthreshold swings comparable to conventional metal/oxide wrap-gated nanowire transistors. Patterning eliminates gate/contact overlap, which reduces parasitic effects and enables multiple, independently controllable gates. The method's simplicity broadens the scope for using polymer electrolyte gating in studies of nanowires and other nanoscale devices. © 2013 American Chemical Society.

Field programmable gate array based predictive control system for spacecraft rendezvous in elliptical orbits

Copyright © 2014 John Wiley & Sons, Ltd. Copyright © 2014 John Wiley & Sons, Ltd. Summary A field programmable gate array (FPGA) based model predictive controller for two phases of spacecraft rendezvous is presented. Linear time-varying prediction models are used to accommodate elliptical orbits, and a variable prediction horizon is used to facilitate finite time completion of the longer range manoeuvres, whilst a fixed and receding prediction horizon is used for fine-grained tracking at close range. The resulting constrained optimisation problems are solved using a primal-dual interior point algorithm. The majority of the computational demand is in solving a system of simultaneous linear equations at each iteration of this algorithm. To accelerate these operations, a custom circuit is implemented, using a combination of Mathworks HDL Coder and Xilinx System Generator for DSP, and used as a peripheral to a MicroBlaze soft-core processor on the FPGA, on which the remainder of the system is implemented. Certain logic that can be hard-coded for fixed sized problems is implemented to be configurable online, in order to accommodate the varying problem sizes associated with the variable prediction horizon. The system is demonstrated in closed-loop by linking the FPGA with a simulation of the spacecraft dynamics running in Simulink on a PC, using Ethernet. Timing comparisons indicate that the custom implementation is substantially faster than pure embedded software-based interior point methods running on the same MicroBlaze and could be competitive with a pure custom hardware implementation.

A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination

It has been previously observed that thin film transistors (TFTs) utilizing an amorphous indium gallium zinc oxide (a-IGZO) semiconducting channel suffer from a threshold voltage shift when subjected to a negative gate bias and light illumination simultaneously. In this work, a thermalization energy analysis has been applied to previously published data on negative bias under illumination stress (NBIS) in a-IGZO TFTs. A barrier to defect conversion of 0.65-0.75 eV is extracted, which is consistent with reported energies of oxygen vacancy migration. The attempt-to-escape frequency is extracted to be 10 6-107 s-1, which suggests a weak localization of carriers in band tail states over a 20-40 nm distance. Models for the NBIS mechanism based on charge trapping are reviewed and a defect pool model is proposed in which two distinct distributions of defect states exist in the a-IGZO band gap: these are associated with states that are formed as neutrally charged and 2+ charged oxygen vacancies at the time of film formation. In this model, threshold voltage shift is not due to a defect creation process, but to a change in the energy distribution of states in the band gap upon defect migration as this allows a state formed as a neutrally charged vacancy to be converted into one formed as a 2+ charged vacancy and vice versa. Carrier localization close to the defect migration site is necessary for the conversion process to take place, and such defect migration sites are associated with conduction and valence band tail states. Under negative gate bias stressing, the conduction band tail is depleted of carriers, but the bias is insufficient to accumulate holes in the valence band tail states, and so no threshold voltage shift results. It is only under illumination that the quasi Fermi level for holes is sufficiently lowered to allow occupation of valence band tail states. The resulting charge localization then allows a negative threshold voltage shift, but only under conditions of simultaneous negative gate bias and illumination, as observed experimentally as the NBIS effect. © 2014 AIP Publishing LLC.

Parameters influencing the maximum controllable current in gate commutated thyristors

The model of interconnected numerical device segments can give a prediction on the dynamic performance of large area full wafer devices such as the Gate Commutated Thyristors (GCTs) and can be used as an optimisation tool for designing GCTs. In this study the authors evaluate the relative importance of the shallow p-base thickness, its peak concentration, the depth of the p-base and the buffer peak concentration. © The Institution of Engineering and Technology 2014.

Development of high-k gate dielectric materials

The traditional gate dielectric material Of SiO2 can not satisfy the need of the continuous downscaling of CMOS dimensions. High-K gate dielectric materials have attracted extensive research efforts recently and obtained great progress. In this paper, the developments of high-K gate materials were reviewed. Based on the author's background and research work in the area, the latest achievements of high-K gate dielectric materials on the recrystalization temperature, the low-K interface layer, and the dielectric breakdown and metal gate electrode were introduced in detail.

Compact voltage-mode multi-valued literal gate using nanoscale ballistic MOSFETs

A CMOS voltage-mode multi-valued literal gate is presented. The ballistic electron transport characteristic of nanoscale MOSFETs is smartly used to compactly achieve universal radix-4 literal operations. The proposed literal gates have small numbers of transistors and low power dissipations, which makes them promising for future nanoscale multi-valued circuits. The gates are simulated by HSPICE.

High-performance 2 mm gate width GaNHEMTs on 6H-SiC with output power of 22.4 W @ 8 GHz

Optimized AlGaN/AlN/GaN high electron mobility transistors (HEMTs) structures were grown on 2-in semi-insulating (SI) 6H-SiC substrate by metal-organic chemical vapor deposition (MOCVD). The 2-in. HEMT wafer exhibited a low average sheet resistance of 305.3 Omega/sq with a uniformity of 3.85%. The fabricated large periphery device with a dimension of 0.35 pm x 2 nun demonstrated high performance, with a maximum DC current density of 1360 mA/mm, a transconductance of 460 mS/mm, a breakdown voltage larger than 80 V, a current gain cut-off frequency of 24 GHz and a maximum oscillation frequency of 34 GHz. Under the condition of continuous-wave (CW) at 9 GHz, the device achieved 18.1 W output power with a power density of 9.05 W/mm and power-added-efficiency (PAE) of 36.4%. While the corresponding results of pulse condition at 8 GHz are 22.4 W output power with 11.2 W/mm power density and 45.3% PAE. These are the state-of-the-art power performance ever reported for this physical dimension of GaN HEMTs based on SiC substrate at 8 GHz. (c) 2008 Elsevier Ltd. All rights reserved.