A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications

The conventional metal oxide semiconductor field effect transistor (MOSFET)may not be suitable for future low standby power (LSTP) applications due to its high off-state current as the sub-threshold swing is theoretically limited to 60mV/decade. Tunnel field effect transistor (TFET) based on gate controlled band to band tunneling has attracted attention for such applications due to its extremely small sub-threshold swing (much less than 60mV/decade). This paper takes a simulation approach to gain some insight into its electrostatics and the carrier transport mechanism. Using 2D device simulations, a thorough study and analysis of the electrical parameters of the planar double gate TFET is performed. Due to excellent sub-threshold characteristics and a reverse biased structure, it offers orders of magnitude less leakage current compared to the conventional MOSFET. In this work, it is shown that the device can be scaled down to channel lengths as small as 30 nm without affecting its performance. Also, it is observed that the bulk region of the device plays a major role in determining the sub-threshold characteristics of the device and considerable improvement in performance (in terms of ION/IOFF ratio) can be achieved if the thickness of the device is reduced. An ION/IOFF ratio of 2x1012 and a minimum point sub-threshold swing of 22mV/decade is obtained.

An improved sapce phasor based current hysteresis controller with reduced switching frequency variations using variable parabolic bands

A current error space phasor based simple hysteresis controller is proposed in this paper to control the switching frequency variation in two-level pulsewidth-modulation (PWM) inverter-fed induction motor (IM) drives. A parabolic boundary for the current error space phasor is suggested for the first time to obtain the switching frequency spectrum for output voltage with hysteresis controller similar to the constant switching frequency voltage-controlled space vector PWM-based IM drive. A novel concept of online variation of this parabolic boundary, which depends on the operating speed of motor, is presented. A generalized technique that determines the set of unique parabolic boundaries for a two-level inverter feeding any given induction motor is described. The sector change logic is self-adaptive and is capable of taking the drive up to the six-step mode if needed. Steady-state and transient performance of proposed controller is experimentally verified on a 3.7-kW IM drive in the entire speed range. Close resemblance of the simulation and experimental results is shown.

A Multilevel inverter structure with cascaded two level and three level inverters for IM drive with CMV elimination and DC link capacitor voltage balancing

Common mode voltage (CMV) variations in PWM inverter-fed drives generate unwanted shaft and bearing current resulting in early motor failure. Multilevel inverters reduce this problem to some extent, with higher number of levels. But the complexity of the power circuit increases with an increase in the number of inverter voltage levels. In this paper a five-level inverter structure is proposed for open-end winding induction motor (IM) drives, by cascading only two conventional two-level and three-level inverters, with the elimination of the common mode voltage over the entire modulation range. The DC link power supply requirement is also optimized by means of DC link capacitor voltage balancing, with PWM control, using only inverter switching state redundancies. The proposed power circuit gives a simple power bus structure.

A five level inverter scheme with common mode volatge elimination by cascading conventional two level and three level NPC inverters for an induction motor drive

Common-mode voltage generated by the PWM inverter causes shaft voltage, bearing current and ground leakage current in induction motor drive system, resulting in an early motor failure. This paper presents a common-mode elimination scheme for a five-level inverter with reduced power circuit complexity. The proposed scheme is realised by cascading conventional two-level and conventional NPC three-level inverters in conjunction with an open-end winding three-phase induction motor drive and the common-mode voltage (CMV) elimination is achieved by using only switching states that result in zero CMV, for the entire modulation range.

Connectivity-aware Routing in Sensor Networks

Sensor network applications such as environmental monitoring demand that the data collection process be carried out for the longest possible time. Our paper addresses this problem by presenting a routing scheme that ensures that the monitoring network remains connected and hence the live sensor nodes deliver data for a longer duration. We analyze the role of relay nodes (neighbours of the base-station) in maintaining network connectivity and present a routing strategy that, for a particular class of networks, approaches the optimal as the set of relay nodes becomes larger. We then use these findings to develop an appropriate distributed routing protocol using potential-based routing. The basic idea of potential-based routing is to define a (scalar) potential value at each node in the network and forward data to the neighbor with the highest potential. We propose a potential function and evaluate its performance through simulations. The results show that our approach performs better than the well known lifetime maximization policy proposed by Chang and Tassiulas (2004), as well as AODV [Adhoc on demand distance vector routing] proposed by Perkins (1997).

STEM+: A Fair and Efficient Algorithm for Scheduling on the DSCH in UMTS Networks

In Universal Mobile Telecommunication Systems (UMTS), the Downlink Shared Channel (DSCH) can be used for providing streaming services. The traffic model for streaming services is different from the commonly used continuously- backlogged model. Each connection specifies a required service rate over an interval of time, k, called the "control horizon". In this paper, our objective is to determine how k DSCH frames should be shared among a set of I connections. We need a scheduler that is efficient and fair and introduce the notion of discrepancy to balance the conflicting requirements of aggregate throughput and fairness. Our motive is to schedule the mobiles in such a way that the schedule minimizes the discrepancy over the k frames. We propose an optimal and computationally efficient algorithm, called STEM+. The proof of the optimality of STEM+, when applied to the UMTS rate sets is the major contribution of this paper. We also show that STEM+ performs better in terms of both fairness and aggregate throughput compared to other scheduling algorithms. Thus, STEM+ achieves both fairness and efficiency and is therefore an appealing algorithm for scheduling streaming connections.

Packet Reordering in Network Processors

Network processors today consist of multiple parallel processors (micro engines) with support for multiple threads to exploit packet level parallelism inherent in network workloads. With such concurrency, packet ordering at the output of the network processor cannot be guaranteed. This paper studies the effect of concurrency in network processors on packet ordering. We use a validated Petri net model of a commercial network processor, Intel IXP 2400, to determine the extent of packet reordering for IPv4 forwarding application. Our study indicates that in addition to the parallel processing in the network processor, the allocation scheme for the transmit buffer also adversely impacts packet ordering. In particular, our results reveal that these packet reordering results in a packet retransmission rate of up to 61%. We explore different transmit buffer allocation schemes namely, contiguous, strided, local, and global which reduces the packet retransmission to 24%. We propose an alternative scheme, packet sort, which guarantees complete packet ordering while achieving a throughput of 2.5 Gbps. Further, packet sort outperforms the in-built packet ordering schemes in the IXP processor by up to 35%.

An Efficient Scheme for Establishing Pairwise Keys for Wireless Sensor Networks

This paper addresses the problem of secure path key establishment in wireless sensor networks that uses the random key pre-distribution technique. Inspired by the recent proxy-based scheme in the work of Ling and Znati (2005) and Li et al. (2005), we introduce a friend-based scheme for establishing pairwise keys securely. We show that the chances of finding friends in a neighbourhood are considerably more than that of finding proxies, leading to lower communication overhead. Further, we prove that the friend-based scheme performs better than the proxy-based scheme both in terms of resilience against node capture as well as in energy consumption for pairwise key establishment, making our scheme more feasible.