The PiLLoW/Ciao library for INTERNET/WWW programming using computational logic systems

We discuss from a practical point of view a number of issues involved in writing Internet and WWW applications using LP/CLP systems. We describe PiLLoW, an Internet and WWW programming library for LP/CLP systems which we arg��e significantly simplifies the process of writing such applications. PiLLoW provides facilities for generating HTML structured documents, producing HTML forms, writing form handlers, accessing and parsing WWW documents, and accessing code posted at HTTP addresses. We also describe the architecture of some application classes, using a high-level model of client-server interaction, active modules. Finally we describe an architecture for automatic LP/CLP code downloading for local execution, using generic browsers. The PiLLoW library has been developed in the context of the &-Prolog and CIAO systems, but it has been adapted to a number of popular LP/CLP systems, supporting most of its functionality.

On the uses of attributed variables in parallel and concurrent logic programming systems

Incorporating the possibility of attaching attributes to variables in a logic programming system has been shown to allow the addition of general constraint solving capabilities to it. This approach is very attractive in that by adding a few primitives any logic programming system can be turned into a generic constraint logic programming system in which constraint solving can be user defined, and at source level - an extreme example of the "glass box" approach. In this paper we propose a different and novel use for the concept of attributed variables: developing a generic parallel/concurrent (constraint) logic programming system, using the same "glass box" flavor. We arg��e that a system which implements attributed variables and a few additional primitives can be easily customized at source level to implement many of the languages and execution models of parallelism and concurrency currently proposed, in both shared memory and distributed systems. We illustrate this through examples.

Implementation of an event driven scheme for visualizing parallel execution of logic programs

This article presents in an informal way some early results on the design of a series of paradigms for visualization of the parallel execution of logic programs. The results presented here refer to the visualization of or-parallelism, as in MUSE and Aurora, deterministic dependent and-parallelism, as in Andorra-I, and independent and-parallelism as in &-Prolog. A tool has been implemented for this purpose and has been interfaced with these systems. Results are presented showing the visualization of executions from these systems and the usefulness of the resulting tool is briefly discussed.

An abstract machine based execution model for computer architecture design and efficient implementation of logic programs in parallel.

The term "Logic Programming" refers to a variety of computer languages and execution models which are based on the traditional concept of Symbolic Logic. The expressive power of these languages offers promise to be of great assistance in facing the programming challenges of present and future symbolic processing applications in Artificial Intelligence, Knowledge-based systems, and many other areas of computing. The sequential execution speed of logic programs has been greatly improved since the advent of the first interpreters. However, higher inference speeds are still required in order to meet the demands of applications such as those contemplated for next generation computer systems. The execution of logic programs in parallel is currently considered a promising strategy for attaining such inference speeds. Logic Programming in turn appears as a suitable programming paradigm for parallel architectures because of the many opportunities for parallel execution present in the implementation of logic programs. This dissertation presents an efficient parallel execution model for logic programs. The model is described from the source language level down to an "Abstract Machine" level suitable for direct implementation on existing parallel systems or for the design of special purpose parallel architectures. Few assumptions are made at the source language level and therefore the techniques developed and the general Abstract Machine design are applicable to a variety of logic (and also functional) languages. These techniques offer efficient solutions to several areas of parallel Logic Programming implementation previously considered problematic or a source of considerable overhead, such as the detection and handling of variable binding conflicts in AND-Parallelism, the specification of control and management of the execution tree, the treatment of distributed backtracking, and goal scheduling and memory management issues, etc. A parallel Abstract Machine design is offered, specifying data areas, operation, and a suitable instruction set. This design is based on extending to a parallel environment the techniques introduced by the Warren Abstract Machine, which have already made very fast and space efficient sequential systems a reality. Therefore, the model herein presented is capable of retaining sequential execution speed similar to that of high performance sequential systems, while extracting additional gains in speed by efficiently implementing parallel execution. These claims are supported by simulations of the Abstract Machine on sample programs.

Detecting common scientific workflow fragments using templates and execution provenance

Provenance plays a major role when understanding and reusing the methods applied in a scientic experiment, as it provides a record of inputs, the processes carried out and the use and generation of intermediate and nal results. In the specic case of in-silico scientic experiments, a large variety of scientic workflow systems (e.g., Wings, Taverna, Galaxy, Vistrails) have been created to support scientists. All of these systems produce some sort of provenance about the executions of the workflows that encode scientic experiments. However, provenance is normally recorded at a very low level of detail, which complicates the understanding of what happened during execution. In this paper we propose an approach to automatically obtain abstractions from low-level provenance data by finding common workflow fragments on workflow execution provenance and relating them to templates. We have tested our approach with a dataset of workflows published by the Wings workflow system. Our results show that by using these kinds of abstractions we can highlight the most common abstract methods used in the executions of a repository, relating different runs and workflow templates with each other.

Implementation of an event driven scheme for visualizing parallel execution of logic programs.

This article presents in an informal way some early results on the design of a series of paradigms for visualization of the parallel execution of logic programs. The results presented here refer to the visualization of or-parallelism, as in MUSE and Aurora, deterministic dependent and-parallelism, as in Andorra-I, and independent and-parallelism as in &-Prolog. A tool has been implemented for this purpose and has been interfaced with these systems. Results are presented showing the visualization of executions from these systems and the usefulness of the resulting tool is briefly discussed.

A proposal for a flexible scheduling and memory management scheme for non-deterministic, andparallel execution of logic programs

In this paper, we examine the issue of memory management in the parallel execution of logic programs. We concentrate on non-deterministic and-parallel schemes which we believe present a relatively general set of problems to be solved, including most of those encountered in the memory management of or-parallel systems. We present a distributed stack memory management model which allows flexible scheduling of goals. Previously proposed models (based on the "Marker model") are lacking in that they impose restrictions on the selection of goals to be executed or they may require consume a large amount of virtual memory. This paper first presents results which imply that the above mentioned shortcomings can have significant performance impacts. An extension of the Marker Model is then proposed which allows flexible scheduling of goals while keeping (virtual) memory consumption down. Measurements are presented which show the advantage of this solution. Methods for handling forward and backward execution, cut and roll back are discussed in the context of the proposed scheme. In addition, the paper shows how the same mechanism for flexible scheduling can be applied to allow the efficient handling of the very general form of suspension that can occur in systems which combine several types of and-parallelism and more sophisticated methods of executing logic programs. We believe that the results are applicable to many and- and or-parallel systems.

Super resolution using a modified Spherical Geodesic Waveguide suitable for manufacturing

The previous publications (Mi��ano et al, 2011) have shown that using a Spherical Geodesic Waveguide (SGW), it can be achieved the super-resolution up to ? /500 close to a set of discrete frequencies. These frequencies are directly connected with the well-known Schumann resonance frequencies of spherical symmetric systems. However, the Spherical Geodesic Waveguide (SGW) has been presented as an ideal system, in which the technological obstacles or manufacturing feasibility and their influence on final results were not taken into account. In order to prove the concept of superresolution experimentally, the Spherical Geodesic Waveguide is modified according to the manufacturing requirements and technological limitations. Each manufacturing process imposes some imperfections which can affect the experimental results. Here, we analyze the influence of the manufacturing limitations on the super-resolution properties of the SGW. Beside the theoretical work, herein, there has been presented the experimental results, as well.

Behaviour Driven Development for Multi-Agent Systems

This paper presents a testing methodology to apply Behaviour Driven Development (BDD) techniques while developing Multi-Agent Systems (MAS), so called BEhavioural Agent Simple Testing (BEAST) methodology. It is supported by the developed open source framework (BEAST Tool) which automatically generates test cases skeletons from BDD scenarios specifications. The developed framework allows testing MASs based on JADE or JADEX platforms and offers a set of configurable Mock Agents which allow the execution of tests while the system is under development. BEAST tool has been validated in the development of a MAS for fault diagnosis in FTTH (Fiber To The Home) networks.

Optical systems design using the SMS method and optimizations

Resumen El dise��o de sistemas ��pticos, entendido como un arte por algunos, como una ciencia por otros, se ha realizado durante siglos. Desde los egipcios hasta nuestros d��as los sistemas de formaci��n de imagen han ido evolucionando as�� como las t��cnicas de dise��o asociadas. Sin embargo ha sido en los ��ltimos 50 a��os cuando las t��cnicas de dise��o han experimentado su mayor desarrollo y evoluci��n, debido, en parte, a la aparici��n de nuevas t��cnicas de fabricaci��n y al desarrollo de ordenadores cada vez m��s potentes que han permitido el c��lculo y an��lisis del trazado de rayos a trav��s de los sistemas ��pticos de forma r��pida y eficiente. Esto ha propiciado que el dise��o de sistemas ��pticos evolucione desde los dise��os desarrollados ��nicamente a partir de la ��ptica paraxial hasta lo modernos dise��os realizados mediante la utilizaci��n de diferentes t��cnicas de optimizaci��n multiparam��trica. El principal problema con el que se encuentra el dise��ador es que las diferentes t��cnicas de optimizaci��n necesitan partir de un dise��o inicial el cual puede fijar las posibles soluciones. Dicho de otra forma, si el punto de inicio est�� lejos del m��nimo global, o dise��o ��ptimo para las condiciones establecidas, el dise��o final puede ser un m��nimo local cerca del punto de inicio y lejos del m��nimo global. Este tipo de problem��tica ha llevado al desarrollo de sistemas globales de optimizaci��n que cada vez sean menos sensibles al punto de inicio de la optimizaci��n. Aunque si bien es cierto que es posible obtener buenos dise��os a partir de este tipo de t��cnicas, se requiere de muchos intentos hasta llegar a la soluci��n deseada, habiendo un entorno de incertidumbre durante todo el proceso, puesto que no est�� asegurado el que se llegue a la soluci��n ��ptima. El m��todo de las Superficies M��ltiples Simultaneas (SMS), que naci�� como una herramienta de c��lculo de concentradores anid��licos, se ha demostrado como una herramienta tambi��n capaz utilizarse para el dise��o de sistemas ��pticos formadores de imagen, aunque hasta la fecha se ha utilizado para el dise��o puntual de sistemas de formaci��n de imagen. Esta tesis tiene por objeto presentar el SMS como un m��todo que puede ser utilizado de forma general para el dise��o de cualquier sistema ��ptico de focal fija o v afocal con un aumento definido as�� como una herramienta que puede industrializarse para ayudar al dise��ador a afrontar de forma sencilla el dise��o de sistemas ��pticos complejos. Esta tesis est�� estructurada en cinco cap��tulos: El cap��tulo 1, es un cap��tulo de fundamentos donde se presentan los conceptos fundamentales necesarios para que el lector, aunque no posea una gran base en ��ptica formadora de imagen, pueda entender los planteamientos y resultados que se presentan en el resto de cap��tulos El capitulo 2 aborda el problema de la optimizaci��n de sistemas ��pticos, donde se presenta el m��todo SMS como una herramienta id��nea para obtener un punto de partida para el proceso de optimizaci��n. Mediante un ejemplo aplicado se demuestra la importancia del punto de partida utilizado en la soluci��n final encontrada. Adem��s en este cap��tulo se presentan diferentes t��cnicas que permiten la interpolaci��n y optimizaci��n de las superficies obtenidas a partir de la aplicaci��n del SMS. Aunque en esta tesis se trabajar�� ��nicamente utilizando el SMS2D, se presenta adem��s un m��todo para la interpolaci��n y optimizaci��n de las nubes de puntos obtenidas a partir del SMS3D basado en funciones de base radial (RBF). En el cap��tulo 3 se presenta el dise��o, fabricaci��n y medidas de un objetivo catadi��ptrico panor��mico dise��ado para trabajar en la banda del infrarrojo lejano (8-12 ��m) para aplicaciones de vigilancia perimetral. El objetivo presentado se dise��a utilizando el m��todo SMS para tres frentes de onda de entrada utilizando cuatro superficies. La potencia del m��todo de dise��o utilizado se hace evidente en la sencillez con la que este complejo sistema se dise��a. Las im��genes presentadas demuestran c��mo el prototipo desarrollado cumple a la perfecci��n su prop��sito. El cap��tulo 4 aborda el problema del dise��o de sistemas ��pticos ultra compactos, se introduce el concepto de sistemas multicanal, como aquellos sistemas ��pticos compuestos por una serie de canales que trabajan en paralelo. Este tipo de sistemas resultan particularmente id��neos para ��l dise��o de sistemas afocales. Se presentan estrategias de dise��o para sistemas multicanal tanto monocrom��ticos como policrom��ticos. Utilizando la novedosa t��cnica de dise��o que en este cap��tulo se presenta el dise��o de un telescopio de seis aumentos y medio. En el cap��tulo 5 se presenta una generalizaci��n del m��todo SMS para rayos meridianos. En este cap��tulo se presenta el algoritmo que debe utilizarse para el dise��o de cualquier sistema ��ptico de focal fija. La denominada optimizaci��n fase 1 se vi introduce en el algoritmo presentado de forma que mediante el cambio de las condiciones in��ciales del dise��o SMS que, aunque el dise��o se realice para rayos meridianos, los rayos skew tengan un comportamiento similar. Para probar la potencia del algoritmo desarrollado se presenta un conjunto de dise��os con diferente n��mero de superficies. La estabilidad y potencia del algoritmo se hace evidente al conseguirse por primera vez el dise��o de un sistema de seis superficies dise��ado por SMS. vii Abstract The design of optical systems, considered an art by some and a science by others, has been developed for centuries. Imaging optical systems have been evolving since Ancient Egyptian times, as have design techniques. Nevertheless, the most important developments in design techniques have taken place over the past 50 years, in part due to the advances in manufacturing techniques and the development of increasingly powerful computers, which have enabled the fast and efficient calculation and analysis of ray tracing through optical systems. This has led to the design of optical systems evolving from designs developed solely from paraxial optics to modern designs created by using different multiparametric optimization techniques. The main problem the designer faces is that the different optimization techniques require an initial design which can set possible solutions as a starting point. In other words, if the starting point is far from the global minimum or optimal design for the set conditions, the final design may be a local minimum close to the starting point and far from the global minimum. This type of problem has led to the development of global optimization systems which are increasingly less sensitive to the starting point of the optimization process. Even though it is possible to obtain good designs from these types of techniques, many attempts are necessary to reach the desired solution. This is because of the uncertain environment due to the fact that there is no guarantee that the optimal solution will be obtained. The Simultaneous Multiple Surfaces (SMS) method, designed as a tool to calculate anidolic concentrators, has also proved useful for the design of image-forming optical systems, although until now it has occasionally been used for the design of imaging systems. This thesis aims to present the SMS method as a technique that can be used in general for the design of any optical system, whether with a fixed focal or an afocal with a defined magnification, and also as a tool that can be commercialized to help designers in the design of complex optical systems. The thesis is divided into five chapters. Chapter 1 establishes the basics by presenting the fundamental concepts which the reader needs to acquire, even if he/she doesn���t have extensive knowledge in the field viii of image-forming optics, in order to understand the steps taken and the results obtained in the following chapters. Chapter 2 addresses the problem of optimizing optical systems. Here the SMS method is presented as an ideal tool to obtain a starting point for the optimization process. The importance of the starting point for the final solution is demonstrated through an example. Additionally, this chapter introduces various techniques for the interpolation and optimization of the surfaces obtained through the application of the SMS method. Even though in this thesis only the SMS2D method is used, we present a method for the interpolation and optimization of clouds of points obtained though the SMS3D method, based on radial basis functions (RBF). Chapter 3 presents the design, manufacturing and measurement processes of a catadioptric panoramic lens designed to work in the Long Wavelength Infrared (LWIR) (8-12 microns) for perimeter surveillance applications. The lens presented is designed by using the SMS method for three input wavefronts using four surfaces. The powerfulness of the design method used is revealed through the ease with which this complex system is designed. The images presented show how the prototype perfectly fulfills its purpose. Chapter 4 addresses the problem of designing ultra-compact optical systems. The concept of multi-channel systems, such as optical systems composed of a series of channels that work in parallel, is introduced. Such systems are especially suitable for the design of afocal systems. We present design strategies for multichannel systems, both monochromatic and polychromatic. A telescope designed with a magnification of six-and-a-half through the innovative technique exposed in this chapter is presented. Chapter 5 presents a generalization of the SMS method for meridian rays. The algorithm to be used for the design of any fixed focal optics is revealed. The optimization known as phase 1 optimization is inserted into the algorithm so that, by changing the initial conditions of the SMS design, the skew rays have a similar behavior, despite the design being carried out for meridian rays. To test the power of the developed algorithm, a set of designs with a different number of surfaces is presented. The stability and strength of the algorithm become apparent when the first design of a system with six surfaces if obtained through the SMS method.

Free-form optical systems for nonimaging applications : Sistemas ��pticos anam��rficos para aplicaciones anid��licas

La ��ptica anid��lica es una rama de la ��ptica cuyo desarrollo comenz�� a mediados de la d��cada de 1960. Este relativamente nuevo campo de la ��ptica se centra en la transferencia eficiente de la luz, algo necesario en muchas aplicaciones, entre las que destacamos los concentradores solares y los sistemas de iluminaci��n. Las soluciones de la ��ptica cl��sica a los problemas de la transferencia de energ��a de la luz s��lo son adecuadas cuando los rayos de luz son paraxiales. La condici��n paraxial no se cumple en la mayor��a de las aplicaciones para concentraci��n e iluminaci��n. Esta tesis contiene varios dise��os free-form (aquellos que no presentan ninguna simetr��a, ni de rotaci��n ni lineal) cuyas aplicaciones van destinadas a estos dos campos. El t��rmino nonimaging viene del hecho de que estos sistemas ��pticos no necesitan formar una imagen del objeto, aunque no formar la imagen no es una condici��n necesaria. Otra palabra que se utiliza a veces en lugar de nonimaging es la palabra anid��lico, viene del griego "an+eidolon" y tiene el mismo significado. La mayor��a de los sistemas ��pticos dise��ados para aplicaciones anid��licas no presentan ninguna simetr��a, es decir, son free-form (anam��rficos). Los sistemas ��pticos free-form est��n siendo especialmente relevantes durante los ��ltimos a��os gracias al desarrollo de las herramientas para su fabricaci��n como m��quinas de moldeo por inyecci��n y el mecanizado multieje. Sin embargo, solo recientemente se han desarrollado t��cnicas de dise��o anid��licas capaces de cumplir con estos grados de libertad. En aplicaciones de iluminaci��n el m��todo SMS3D permite dise��ar dos superficies free-form para controlar las fuentes de luz extensas. En los casos en que se requiere una elevada asimetr��a de la fuente, el objeto o las restricciones volum��tricos, las superficies free-form permiten obtener soluciones de mayor eficiencia, o disponer de menos elementos en comparaci��n con las soluciones de simetr��a de rotaci��n, dado que las superficies free-form tienen m��s grados de libertad y pueden realizar m��ltiples funciones debido a su naturaleza anam��rfica. Los concentradores anid��licos son muy adecuados para la captaci��n de energ��a solar, ya que el objetivo no es la reproducci��n de una imagen exacta del sol, sino sencillamente la captura de su energ��a. En este momento, el campo de la concentraci��n fotovoltaica (CPV) tiende hacia sistemas de alta concentraci��n con el fin de compensar el gasto de las c��lulas solares multi-uni��n (MJ) utilizadas como receptores, reduciendo su ��rea. El inter��s en el uso de c��lulas MJ radica en su alta eficiencia de conversi��n. Para obtener sistemas competitivos en aplicaciones terrestres se recurre a sistemas fotovoltaicos de alta concentraci��n (HCPV), con factores de concentraci��n geom��trica por encima de 500x. Estos sistemas se componen de dos (o m��s) elementos ��pticos (espejos y/o lentes). En los sistemas presentados a lo largo de este trabajo se presentan ejemplos de concentradores HCPV con elementos reflexivos como etapa primaria, as�� como concentradores con elementos refractivos (lente de Fresnel). Con la necesidad de aumentar la eficiencia de los sistemas HCPV reales y con el fin de proporcionar la divisi��n m��s eficiente del espectro solar, c��lulas conteniendo cuatro o m��s uniones (con un potencial de alcanzar eficiencias de m��s del 45% a una concentraci��n de cientos de soles) se exploran hoy en d��a. En esta tesis se presenta una de las posibles arquitecturas de divisi��n del espectro (spectrum-splitting en la literatura anglosajona) que utilizan c��lulas de concentraci��n comercial. Otro campo de aplicaci��n de la ��ptica nonimaging es la iluminaci��n, donde es necesario proporcionar un patr��n de distribuci��n de la iluminaci��n espec��fico. La iluminaci��n de estado s��lido (SSL), basada en la electroluminiscencia de materiales semiconductores, est�� proporcionando fuentes de luz para aplicaciones de iluminaci��n general. En la ��ltima d��cada, los diodos emisores de luz (LED) de alto brillo han comenzado a reemplazar a las fuentes de luz convencionales debido a la superioridad en la calidad de la luz emitida, elevado tiempo de vida, compacidad y ahorro de energ��a. Los colimadores utilizados con LEDs deben cumplir con requisitos tales como tener una alta eficiencia, un alto control del haz de luz, una mezcla de color espacial y una gran compacidad. Presentamos un colimador de luz free-form con microestructuras capaz de conseguir buena colimaci��n y buena mezcla de colores con una fuente de LED RGGB. Una buena mezcla de luz es importante no s��lo para simplificar el dise��o ��ptico de la luminaria sino tambi��n para evitar hacer binning de los chips. La mezcla de luz ��ptica puede reducir los costes al evitar la modulaci��n por ancho de pulso y otras soluciones electr��nicas patentadas para regulaci��n y ajuste de color. Esta tesis consta de cuatro cap��tulos. Los cap��tulos que contienen la obra original de esta tesis son precedidos por un cap��tulo introductorio donde se presentan los conceptos y definiciones b��sicas de la ��ptica geom��trica y en el cual se engloba la ��ptica nonimaging. Contiene principios de la ��ptica no formadora de imagen junto con la descripci��n de sus problemas y m��todos de dise��o. Asimismo se describe el m��todo de Superficies M��ltiples Simult��neas (SMS), que destaca por su versatilidad y capacidad de controlar varios haces de rayos. Adicionalmente tambi��n se describe la integraci��n K��hler y sus aplicaciones en el campo de la energ��a fotovoltaica. La concentraci��n fotovoltaica y la iluminaci��n de estado s��lido son introducidas junto con la revisi��n de su estado actual. El Segundo y Tercer Cap��tulo contienen dise��os ��pticos avanzados con aplicaci��n en la concentraci��n solar principalmente, mientras que el Cuarto Cap��tulo describe el colimador free-form con surcos que presenta buena mezcla de colores para aplicaciones de iluminaci��n. El Segundo Cap��tulo describe dos concentradores ��pticos HCPV dise��ados con el m��todo SMS en tres dimensiones (SMS3D) que llevan a cabo integraci��n K��hler en dos direcciones con el fin de proporcionar una distribuci��n de irradiancia uniforme libre de aberraciones crom��ticas sobre la c��lula solar. Uno de los dise��os es el concentrador XXR free-form dise��ado con el m��todo SMS3D, donde el espejo primario (X) y la lente secundaria (R) se dividen en cuatro sectores sim��tricos y llevan a cabo la integraci��n K��hler (proporcionando cuatro unidades del array K��hler), mientras que el espejo intermedio (X) presenta simetr��a rotacional. Otro concentrador HCPV presentado es el Fresnel-RXI (FRXI) con una lente de Fresnel funcionando como elemento primario (POE) y una lente RXI como elemento ��ptico secundario (SOE), que presenta configuraci��n 4-fold con el fin de realizar la integraci��n K��hler. Las lentes RXI son dispositivos nonimaging conocidos, pero su aplicaci��n como elemento secundario es novedosa. Los concentradores XXR y FRXI K��hler son ejemplos acad��micos de muy alta concentraci��n (m��s de 2,000x, mientras que los sistemas convencionales hoy en d��a no suelen llegar a 1,000x) preparados para las c��lulas solares N-uni��n (con N>3), que probablemente requerir��n una mayor concentraci��n y alta uniformidad espectral de irradiancia con el fin de obtener sistemas CPV terrestres eficientes y rentables. Ambos concentradores est��n dise��ados maximizando funciones de m��rito como la eficiencia ��ptica, el producto concentraci��n-aceptancia (CAP) y la uniformidad de irradiancia sobre la c��lula libre de la aberraci��n crom��tica (integraci��n K��hler). El Tercer Cap��tulo presenta una arquitectura para la divisi��n del espectro solar basada en un m��dulo HCPV con alta concentraci��n (500x) y ��ngulo de aceptancia alto (���>���1��) que tiene por objeto reducir ambas fuentes de p��rdidas de las c��lulas triple uni��n (3J) comerciales: el uso eficiente del espectro solar y la luz reflejada de los contactos met��licos y de la superficie de semiconductor. El m��dulo para la divisi��n del espectro utiliza el espectro solar m��s eficiente debido a la combinaci��n de una alta eficiencia de una c��lula de concentraci��n 3J (GaInP/GaInAs/Ge) y una de contacto posterior (BPC) de concentraci��n de silicio (Si), as�� como la t��cnica de confinamiento externo para la recuperaci��n de la luz reflejada por la c��lula 3J con el fin de ser reabsorbida por la c��lula. En la arquitectura propuesta, la c��lula 3J opera con su ganancia de corriente optimizada (concentraci��n geom��trica de 500x), mientras que la c��lula de silicio trabaja cerca de su ��ptimo tambi��n (135x). El m��dulo de spectrum-splitting consta de una lente de Fresnel plana como POE y un concentrador RXI free-form como SOE con un filtro paso-banda integrado en ��l. Tanto POE como SOE realizan la integraci��n K��hler para producir homogeneizaci��n de luz sobre la c��lula. El filtro paso banda env��a los fotones IR en la banda 900-1,150nm a la c��lula de silicio. Hay varios aspectos pr��cticos de la arquitectura del m��dulo presentado que ayudan a reducir la complejidad de los sistemas spectrum-splitting (el filtro y el secundario forman una sola pieza s��lida, ambas c��lulas son coplanarias simplific��ndose el cableado y la disipaci��n de calor, etc.). Prototipos prueba-de-concepto han sido ensamblados y probados a fin de demostrar la fabricabilidad del filtro y su rendimiento cuando se combina con la t��cnica de reciclaje de luz externa. Los resultados obtenidos se ajustan bastante bien a los modelos y a las simulaciones e invitan al desarrollo de una versi��n m��s compleja de este prototipo en el futuro. Dos colimadores s��lidos con surcos free-form se presentan en el Cuarto Cap��tulo. Ambos dise��os ��pticos est��n dise��ados originalmente usando el m��todo SMS3D. La segunda superficie ��pticamente activa est�� dise��ada a posteriori como una superficie con surcos. El dise��o inicial de dos espejos (XX) est�� dise��ado como prueba de concepto. En segundo lugar, el dise��o RXI free-form es comparable con los colimadores RXI existentes. Se trata de un dise��o muy compacto y eficiente que proporciona una muy buena mezcla de colores cuando funciona con LEDs RGB fuera del eje ��ptico como en los RGB LEDs convencionales. Estos dos dise��os son dispositivos free-form dise��ados con la intenci��n de mejorar las propiedades de mezcla de colores de los dispositivos no aplan��ticos RXI con simetr��a de revoluci��n y la eficiencia de los aplan��ticos, logrando una buena colimaci��n y una buena mezcla de colores. La capacidad de mezcla de colores del dispositivo no-aplan��tico mejora a��adiendo caracter��sticas de un aplan��tico a su hom��logo sim��trico sin p��rdida de eficiencia. En el caso del dise��o basado en RXI, su gran ventaja consiste en su menor coste de fabricaci��n ya que el proceso de metalizaci��n puede evitarse. Aunque algunos de los componentes presentan formas muy complejas, los costes de fabricaci��n son relativamente insensibles a la complejidad del molde, especialmente en el caso de la producci��n en masa (tales como inyecci��n de pl��stico), ya que el coste del molde se reparte entre todas las piezas fabricadas. Por ��ltimo, las ��ltimas dos secciones son las conclusiones y futuras l��neas de investigaci��n. ABSTRACT Nonimaging optics is a branch of optics whose development began in the mid-1960s. This rather new field of optics focuses on the efficient light transfer necessary in many applications, among which we highlight solar concentrators and illumination systems. The classical optics solutions to the problems of light energy transfer are only appropriate when the light rays are paraxial. The paraxial condition is not met in most applications for the concentration and illumination. This thesis explores several free-form designs (with neither rotational nor linear symmetry) whose applications are intended to cover the above mentioned areas and more. The term nonimaging comes from the fact that these optical systems do not need to form an image of the object, although it is not a necessary condition not to form an image. Another word sometimes used instead of nonimaging is anidolic, and it comes from the Greek ���an+eidolon��� and has the same meaning. Most of the optical systems designed for nonimaging applications are without any symmetry, i.e. free-form. Free-form optical systems become especially relevant lately with the evolution of free-form tooling (injection molding machines, multi-axis machining techniques, etc.). Nevertheless, only recently there are nonimaging design techniques that are able to meet these degrees of freedom. In illumination applications, the SMS3D method allows designing two free-form surfaces to control very well extended sources. In cases when source, target or volumetric constrains have very asymmetric requirements free-form surfaces are offering solutions with higher efficiency or with fewer elements in comparison with rotationally symmetric solutions, as free-forms have more degrees of freedom and they can perform multiple functions due to their free-form nature. Anidolic concentrators are well suited for the collection of solar energy, because the goal is not the reproduction of an exact image of the sun, but instead the collection of its energy. At this time, Concentration Photovoltaics (CPV) field is turning to high concentration systems in order to compensate the expense of multi-junction (MJ) solar cells used as receivers by reducing its area. Interest in the use of MJ cells lies in their very high conversion efficiency. High Concentration Photovoltaic systems (HCPV) with geometric concentration of more than 500x are required in order to have competitive systems in terrestrial applications. These systems comprise two (or more) optical elements, mirrors and/or lenses. Systems presented in this thesis encompass both main types of HCPV architectures: concentrators with primary reflective element and concentrators with primary refractive element (Fresnel lens). Demand for the efficiency increase of the actual HCPV systems as well as feasible more efficient partitioning of the solar spectrum, leads to exploration of four or more junction solar cells or submodules. They have a potential of reaching over 45% efficiency at concentration of hundreds of suns. One possible architectures of spectrum splitting module using commercial concentration cells is presented in this thesis. Another field of application of nonimaging optics is illumination, where a specific illuminance distribution pattern is required. The Solid State Lighting (SSL) based on semiconductor electroluminescence provides light sources for general illumination applications. In the last decade high-brightness Light Emitting Diodes (LEDs) started replacing conventional light sources due to their superior output light quality, unsurpassed lifetime, compactness and energy savings. Collimators used with LEDs have to meet requirements like high efficiency, high beam control, color and position mixing, as well as a high compactness. We present a free-form collimator with microstructures that performs good collimation and good color mixing with RGGB LED source. Good light mixing is important not only for simplifying luminaire optical design but also for avoiding die binning. Optical light mixing may reduce costs by avoiding pulse-width modulation and other patented electronic solutions for dimming and color tuning. This thesis comprises four chapters. Chapters containing the original work of this thesis are preceded by the introductory chapter that addresses basic concepts and definitions of geometrical optics on which nonimaging is developed. It contains fundamentals of nonimaging optics together with the description of its design problems, principles and methods, and with the Simultaneous Multiple Surface (SMS) method standing out for its versatility and ability to control several bundles of rays. K��hler integration and its applications in the field of photovoltaics are described as well. CPV and SSL fields are introduced together with the review on their background and their current status. Chapter 2 and Chapter 3 contain advanced optical designs with primarily application in solar concentration; meanwhile Chapter 4 portrays the free-form V-groove collimator with good color mixing property for illumination application. Chapter 2 describes two HCPV optical concentrators designed with the SMS method in three dimensions (SMS3D). Both concentrators represent K��hler integrator arrays that provide uniform irradiance distribution free from chromatic aberrations on the solar cell. One of the systems is the XXR free-form concentrator designed with the SMS3D method. The primary mirror (X) of this concentrator and secondary lens (R) are divided in four symmetric sectors (folds) that perform K��hler integration; meanwhile the intermediate mirror (X) is rotationally symmetric. Second HCPV concentrator is the Fresnel-RXI (FRXI) with flat Fresnel lens as the Primary Optical Element (POE) and an RXI lens as the Secondary Optical Element (SOE). This architecture manifests 4-fold configuration for performing K��hler integration (4 array units), as well. The RXI lenses are well-known nonimaging devices, but their application as SOE is novel. Both XXR and FRXI K��hler HCPV concentrators are academic examples of very high concentration (more than 2,000x meanwhile conventional systems nowadays have up to 1,000x) prepared for the near future N-junction (N>3) solar cells. In order to have efficient and cost-effective terrestrial CPV systems, those cells will probably require higher concentrations and high spectral irradiance uniformity. Both concentrators are designed by maximizing merit functions: the optical efficiency, concentration-acceptance angle (CAP) and cell-irradiance uniformity free from chromatic aberrations (K��hler integration). Chapter 3 presents the spectrum splitting architecture based on a HCPV module with high concentration (500x) and high acceptance angle (���>���1��). This module aims to reduce both sources of losses of the actual commercial triple-junction (3J) solar cells with more efficient use of the solar spectrum and with recovering the light reflected from the 3J cells��� grid lines and semiconductor surface. The solar spectrum is used more efficiently due to the combination of a high efficiency 3J concentration cell (GaInP/GaInAs/Ge) and external Back-Point-Contact (BPC) concentration silicon (Si) cell. By employing external confinement techniques, the 3J cell���s reflections are recovered in order to be re-absorbed by the cell. In the proposed concentrator architecture, the 3J cell operates at its optimized current gain (at geometrical concentration of 500x), while the Si cell works near its optimum, as well (135x). The spectrum splitting module consists of a flat Fresnel lens (as the POE), and a free-form RXI-type concentrator with a band-pass filter embedded in it (as the SOE), both POE and SOE performing K��hler integration to produce light homogenization. The band-pass filter sends the IR photons in the 900-1,150nm band to the Si cell. There are several practical aspects of presented module architecture that help reducing the added complexity of the beam splitting systems: the filter and secondary are forming a single solid piece, both cells are coplanar so the heat management and wiring is simplified, etc. Two proof-of-concept prototypes are assembled and tested in order to prove filter manufacturability and performance, as well as the potential of external light recycling technique. Obtained measurement results agree quite well with models and simulations, and show an opened path to manufacturing of the Fresnel RXI-type secondary concentrator with spectrum splitting strategy. Two free-form solid V-groove collimators are presented in Chapter 4. Both free-form collimators are originally designed with the SMS3D method. The second mirrored optically active surface is converted in a grooved surface a posteriori. Initial two mirror (XX) design is presented as a proof-of-concept. Second, RXI free-form design is comparable with existing RXI collimators as it is a highly compact and a highly efficient design. It performs very good color mixing of the RGGB LED sources placed off-axis like in conventional RGB LEDs. Collimators described here improve color mixing property of the prior art rotationally symmetric no-aplanatic RXI devices, and the efficiency of the aplanatic ones, accomplishing both good collimation and good color mixing. Free-form V-groove collimators enhance the no-aplanatic device's blending capabilities by adding aplanatic features to its symmetric counterpart with no loss in efficiency. Big advantage of the RXI design is its potentially lower manufacturing cost, since the process of metallization may be avoided. Although some components are very complicated for shaping, the manufacturing costs are relatively insensitive to the complexity of the mold especially in the case of mass production (such as plastic injection), as the cost of the mold is spread in many parts. Finally, last two sections are conclusions and future lines of investigation.

NGCPV: a new generation of concentrator photovoltaic cells, modules and systems

Starting on June 2011, NGCPV is the first project funded jointly between the European Commission (EC) and the New Energy and Industrial Technology Development Organization (NEDO) of Japan to research on new generation concentration photovoltaics (CPV). The Project, through a collaborative research between seven European and nine Japanese leading research centers in the field of CPV, aims at lowering the cost of the CPVproduced photovoltaic kWh down to 5 ?cents. The main objective of the project is to improve the present concentrator cell, module and system efficiency, as well as developing advanced characterization tools for CPV components and systems. As particular targets, the project aims at achieving a cell efficiency of at least 45% and a CPV module with an efficiency greater than 35%. This paper describes the R&D activities that are being carried out within the NGCPV project and summarizes some of the most relevant results that have already been attained, for instance: the manufacturing of a 44.4% world record efficiency triple junction solar cell (by Sharp Corp.) and the installation of a 50 kWp experimental CPV plant in Spain, which will be used to obtain accurate forecasts of the energy produced at system level.

Membrane Systems Working with the PFactor: Best Strategy to Solve Complex Problems.

A membrane system is a massive parallel system, which is inspired by the living cells when processing information. As a part of unconventional computing, membrane systems are proven to be effective in solving complex problems. A new factor is introduced. This factor can decide whether a technique is worthwhile being used or not. The use of this factor provides the best chances for selecting the strategy for the rules application phase. Referring to the ���best��� is in reference to the one that reduces execution time within the membrane system. A pre-analysis of the membrane system determines the P-factor, which in return advises the optimal strategy to use. In particular, this paper compares the use of two strategies based on the P-factor and provides results upon the application of them. The paper concludes that the P-factor is an effective indicator for choosing the right strategy to implement the rules application phase in membrane systems.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en t��cnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en ingl��s), que han sido propuestas dentro del campo de investigaci��n acad��mica desde hace 17 a��os. Las investigaciones relacionadas han experimentado un notable crecimiento en las ��ltimas d��cadas, mientras que los dise��os enfocados en la protecci��n s��lida y eficaz contra dichos ataques a��n se mantienen como un tema de investigaci��n abierto, en el que se necesitan iniciativas m��s confiables para la protecci��n de la informaci��n persona de empresa y de datos nacionales. El primer uso documentado de codificaci��n secreta se remonta a alrededor de 1700 B.C., cuando los jerogl��ficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la informaci��n siempre ha supuesto un factor clave en la transmisi��n de datos relacionados con inteligencia diplom��tica o militar. Debido a la evoluci��n r��pida de las t��cnicas modernas de comunicaci��n, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisi��n a trav��s de cables sin seguridad o medios inal��mbricos. Debido a las restricciones de potencia de c��lculo antes de la era del ordenador, la t��cnica de cifrado simple era un m��todo m��s que suficiente para ocultar la informaci��n. Sin embargo, algunas vulnerabilidades algor��tmicas pueden ser explotadas para restaurar la regla de codificaci��n sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el ��rea de la criptograf��a, con el fin de proteger el sistema de informaci��n ante sofisticados algoritmos. Con la invenci��n de los ordenadores se ha acelerado en gran medida la implementaci��n de criptograf��a segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computaci��n altamente reforzadas. Igualmente, sofisticados cripto-an��lisis han impulsado las tecnolog��as de computaci��n. Hoy en d��a, el mundo de la informaci��n ha estado involucrado con el campo de la criptograf��a, enfocada a proteger cualquier campo a trav��s de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificaci��n optimizada de teor��as matem��ticas modernas y pr��cticas eficaces de hardware, siendo posible su implementaci��n en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales m��tricas de conducci��n en el dise��o electr��nico, con el objetivo de promover la fabricaci��n de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementaci��n pr��ctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de an��lisis. Sin embargo, algunas cr��ticas sobre los algoritmos criptogr��ficos te��ricamente seguros surgieron casi inmediatamente despu��s de este descubrimiento. En este sentido, los circuitos digitales consisten t��picamente en un gran n��mero de celdas l��gicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricaci��n. La l��gica de los circuitos se realiza en funci��n de las innumerables conmutaciones de estas c��lulas. Este mecanismo provoca inevitablemente cierta emanaci��n f��sica especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptograf��a de claves), analizar la arquitectura l��gica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparaci��n de correlaci��n entre la cantidad de fuga estimada y las fugas medidas de forma real, informaci��n confidencial puede ser reconstruida en mucho menos tiempo y computaci��n. Para ser precisos, SCA b��sicamente cubre una amplia gama de tipos de ataques, como los an��lisis de consumo de energ��a y radiaci��n ElectroMagn��tica (EM). Ambos se basan en an��lisis estad��stico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no est��n intr��nsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementaci��n de circuitos integrar medidas que permitan camuflar las fugas a trav��s de "canales laterales". Las medidas contra SCA est��n evolucionando junto con el desarrollo de nuevas t��cnicas de ataque, as�� como la continua mejora de los dispositivos electr��nicos. Las caracter��sticas f��sicas requieren contramedidas sobre la capa f��sica, que generalmente se pueden clasificar en soluciones intr��nsecas y extr��nsecas. Contramedidas extr��nsecas se ejecutan para confundir la fuente de ataque mediante la integraci��n de ruido o mala alineaci��n de la actividad interna. Comparativamente, las contramedidas intr��nsecas est��n integradas en el propio algoritmo, para modificar la aplicaci��n con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultaci��n y Enmascaramiento son dos t��cnicas t��picas incluidas en esta categor��a. Concretamente, el enmascaramiento se aplica a nivel algor��tmico, para alterar los datos intermedios sensibles con una m��scara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptograf��as modernas son dif��ciles de enmascarar. Dicho m��todo de ocultaci��n, que ha sido verificado como una soluci��n efectiva, comprende principalmente la codificaci��n en doble carril, que est�� ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, adem��s de la descripci��n de las metodolog��as de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la l��gica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel l��gico. Una caracter��stica de SCA reside en el formato de las fuentes de fugas. Un t��pico ataque de canal lateral se refiere al an��lisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades par��sitas son las fuentes esenciales de fugas. Por lo tanto, una l��gica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas l��gicas b��sicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la l��gica desde un nivel m��s alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones cl��sicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementaci��n de un esquema de dise��o personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el dise��o y la implementaci��n de una l��gica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener din��micamente el equilibrio de las fugas en las capas inferiores; II. Esta l��gica explota las caracter��sticas de la arquitectura de las FPGAs, para reducir al m��nimo el gasto de recursos en la implementaci��n; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo gen��rico de dise��o sobre FPGAs, con el fin de manipular los circuitos de forma autom��tica. El kit de herramientas de dise��o autom��tico es compatible con la l��gica de doble carril propuesta, para facilitar la aplicaci��n pr��ctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodolog��a y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho m��s r��gidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementaci��n y reparaci��n de l��gica de doble carril gen��rica. La viabilidad de las soluciones propuestas es validada mediante la selecci��n de algoritmos criptogr��ficos ampliamente utilizados, y su evaluaci��n exhaustiva en comparaci��n con soluciones anteriores. Todas las propuestas est��n respaldadas eficazmente a trav��s de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigaci��n tiene la intenci��n de cerrar la brecha entre las barreras de implementaci��n y la aplicaci��n efectiva de l��gica de doble carril. En esencia, a lo largo de esta tesis se describir�� un conjunto de herramientas de implementaci��n para FPGAs que se han desarrollado para trabajar junto con el flujo de dise��o gen��rico de las mismas, con el fin de lograr crear de forma innovadora la l��gica de doble carril. Un nuevo enfoque en el ��mbito de la seguridad en el cifrado se propone para obtener personalizaci��n, automatizaci��n y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigaci��n se resumen brevemente a continuaci��n: ������L��gica de Precharge Absorbed-DPL logic: El uso de la conversi��n de netlist para reservar LUTs libres para ejecutar la se��al de precharge y Ex en una l��gica DPL. ������Posicionamiento entrelazado Row-crossed con pares id��nticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medici��n EM selectiva y mitigar los impactos de las variaciones de proceso. ������Ejecuci��n personalizada y herramientas de conversi��n autom��tica para la generaci��n de redes id��nticas para la l��gica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asim��tricas. (c) Para ser utilizado en otras l��gicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. ������Plataforma CPA de pruebas personalizadas para el an��lisis de EM y potencia, incluyendo la construcci��n de dicha plataforma, el m��todo de medici��n y an��lisis de los ataques. ������An��lisis de tiempos para cuantificar los niveles de seguridad. ������Divisi��n de Seguridad en la conversi��n parcial de un sistema de cifrado complejo para reducir los costes de la protecci��n. ������Prueba de concepto de un sistema de calefacci��n auto-adaptativo para mitigar los impactos el��ctricos debido a la variaci��n del proceso de silicio de manera din��mica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuaci��n: En el cap��tulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos b��sicos de teor��a de modelos de an��lisis, adem��s de la implementaci��n de la plataforma y la ejecuci��n de los ataques. En el cap��tulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Adem��s de ello, en este cap��tulo se propone una l��gica en doble carril compacta y segura como contribuci��n de gran relevancia, as�� como tambi��n se presentar�� la transformaci��n l��gica basada en un dise��o a nivel de puerta. Por otra parte, en el Cap��tulo 3 se abordan los desaf��os relacionados con la implementaci��n de l��gica en doble carril gen��rica. As�� mismo, se describir�� un flujo de dise��o personalizado para resolver los problemas de aplicaci��n junto con una herramienta de desarrollo autom��tico de aplicaciones propuesta, para mitigar las barreras de dise��o y facilitar los procesos. En el cap��tulo 4 se describe de forma detallada la elaboraci��n e implementaci��n de las herramientas propuestas. Por otra parte, la verificaci��n y validaciones de seguridad de la l��gica propuesta, as�� como un sofisticado experimento de verificaci��n de la seguridad del rutado, se describen en el cap��tulo 5. Por ��ltimo, un resumen de las conclusiones de la tesis y las perspectivas como l��neas futuras se incluyen en el cap��tulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada cap��tulo se describe de forma m��s detallada a continuaci��n: En el cap��tulo 1 se introduce plataforma de implementaci��n hardware adem��s las teor��as b��sicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura gen��rica y las caracter��sticas de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un m��dulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los m��todos de canal lateral, que permiten revelar las fugas de disipaci��n correlacionadas con los comportamientos internos; y el m��todo para recuperar esta relaci��n entre las fluctuaciones f��sicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del cap��tulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protecci��n de la compensaci��n din��mica de la l��gica gen��rica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripci��n de los elementos compensados a nivel de puerta. En segundo lugar, la l��gica PA-DPL es propuesta como aportaci��n original, detallando el protocolo de la l��gica y un caso de aplicaci��n. En tercer lugar, dos flujos de dise��o personalizados se muestran para realizar la conversi��n de doble carril. Junto con ello, se aclaran las definiciones t��cnicas relacionadas con la manipulaci��n por encima de la netlist a nivel de LUT. Finalmente, una breve discusi��n sobre el proceso global se aborda en la parte final del cap��tulo. El Cap��tulo 3 estudia los principales retos durante la implementaci��n de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantaci��n a trav��s de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos par��sitos, sesgo tecnol��gico y la viabilidad de implementaci��n. De acuerdo con estas elaboraciones, se plantean dos problemas: C��mo implementar la l��gica propuesta sin penalizar los niveles de seguridad, y c��mo manipular un gran n��mero de celdas y automatizar el proceso. El PA-DPL propuesto en el cap��tulo 2 se valida con una serie de iniciativas, desde caracter��sticas estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los m��todos de aplicaci��n tales como las herramientas de personalizaci��n y automatizaci��n de EDA. Por otra parte, un sistema de calefacci��n auto-adaptativo es representado y aplicado a una l��gica de doble n��cleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variaci��n del proceso durante la operaci��n en tiempo real. El cap��tulo 4 se centra en los detalles de la implementaci��n del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la l��gica de circuito post P&R ncd (una versi��n binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y raz��n de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detecci��n de enrutamiento y los enfoques para la reparaci��n. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente id��nticos para la l��gica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este cap��tulo particularmente especifica las bases t��cnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El cap��tulo 5 se enfoca en la aplicaci��n de los casos de estudio para la validaci��n de los grados de seguridad de la l��gica propuesta. Se discuten los problemas t��cnicos detallados durante la ejecuci��n y algunas nuevas t��cnicas de implementaci��n. (a) Se discute el impacto en el proceso de posicionamiento de la l��gica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementaci��n, tomando en cuenta la optimizaci��n global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparaci��n optimizados; (b) las validaciones de seguridad se realizan con los m��todos de correlaci��n y an��lisis de tiempo; (c) Una t��ctica asint��tica se aplica a un n��cleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre m��tricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacci��n auto-adaptativa sobre la variaci��n del proceso son mostrados; (e) Se introduce una aplicaci��n pr��ctica de las herramientas para un dise��o de cifrado completa. Cap��tulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por ��ltimo, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilizaci��n de las contribuciones de esta tesis a un alcance m��s all�� de los dominios de la criptograf��a en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: ������Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. ������A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. ������Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. ���������Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. ������A timing analysis based method for quantifying the security grades. ������A methodology of security partitions of complex crypto systems for reducing the protection cost. ������A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.

Performance measurement integrated information framework in e-Manufacturing

The implementation of Internet technologies has led to e-Manufacturing technologies becoming more widely used and to the development of tools for compiling, transforming and synchronising manufacturing data through the Web. In this context, a potential area for development is the extension of virtual manufacturing to performance measurement (PM) processes, a critical area for decision making and implementing improvement actions in manufacturing. This paper proposes a PM information framework to integrate decision support systems in e-Manufacturing. Specifically, the proposed framework offers a homogeneous PM information exchange model that can be applied through decision support in e-Manufacturing environment. Its application improves the necessary interoperability in decision-making data processing tasks. It comprises three sub-systems: a data model, a PM information platform and PM-Web services architecture. A practical example of data exchange for measurement processes in the area of equipment maintenance is shown to demonstrate the utility of the model.