Cellular DBMS : customizable and autonomous data management using a RISC-style architecture

Magdeburg, Univ., Fak. für Informatik, Diss., 2011

Parallel Architecture Prototype for 60 GHz High Data Rate Wireless Single Carrier Receiver

Nowadays a huge attention of the academia and research teams is attracted to the potential of the usage of the 60 GHz frequency band in the wireless communications. The use of the 60GHz frequency band offers great possibilities for wide variety of applications that are yet to be implemented. These applications also imply huge implementation challenges. Such example is building a high data rate transceiver which at the same time would have very low power consumption. In this paper we present a prototype of Single Carrier -SC transceiver system, illustrating a brief overview of the baseband design, emphasizing the most important decisions that need to be done. A brief overview of the possible approaches when implementing the equalizer, as the most complex module in the SC transceiver, is also presented. The main focus of this paper is to suggest a parallel architecture for the receiver in a Single Carrier communication system. This would provide higher data rates that the communication system canachieve, for a price of higher power consumption. The suggested architecture of such receiver is illustrated in this paper,giving the results of its implementation in comparison with its corresponding serial implementation.

Mapping of the healthy immunoglobulin repertoire over the course of B cell maturation by deep pyrosequencing

Healthy immunoglobulin repertoire has not been extensively evaluated reflecting in part the challenge of generating sufficiently robust data sets by conventional clonal sequencing. Deep sequencing has revolutionized the capacity to evaluate the depth and breadth of the Ig repertoire along the B cell developmental pathway, and can be used to pin point defect(s) of primary or acquired B-cell associated diseases. In this study healthy IgM and IgG repertoires were studied by 454-pyrosequencing to establish the healthy controls for diseased repertoires. (...)

A Novel Memory-centric Architecture and Organization of Processors and Computers

The modern computer systems that are in use nowadays are mostly processor-dominant, which means that their memory is treated as a slave element that has one major task – to serve execution units data requirements. This organization is based on the classical Von Neumann's computer model, proposed seven decades ago in the 1950ties. This model suffers from a substantial processor-memory bottleneck, because of the huge disparity between the processor and memory working speeds. In order to solve this problem, in this paper we propose a novel architecture and organization of processors and computers that attempts to provide stronger match between the processing and memory elements in the system. The proposed model utilizes a memory-centric architecture, wherein the execution hardware is added to the memory code blocks, allowing them to perform instructions scheduling and execution, management of data requests and responses, and direct communication with the data memory blocks without using registers. This organization allows concurrent execution of all threads, processes or program segments that fit in the memory at a given time. Therefore, in this paper we describe several possibilities for organizing the proposed memory-centric system with multiple data and logicmemory merged blocks, by utilizing a high-speed interconnection switching network.

Software for Explicitly Parallel Memory-Centric Processor Architecture

Advances in computer memory technology justify research towards new and different views on computer organization. This paper proposes a novel memory-centric computing architecture with the goal to merge memory and processing elements in order to provide better conditions for parallelization and performance. The paper introduces the architectural concepts and afterwards shows the design and implementation of a corresponding assembler and simulator.

Notes on a collection of Bermuda deep-sea fishes.

v.37:no.9(1955)

Rare fishes of the deep-sea genus Halieutopsis : a review with descriptions of four new species (Lophiiformes; Ogcocephalidae) : a contribution in celebration of the distinguished scholarship of Robert F. Inger on the occasion of his sixty-fifth birthday /

n.s. no.44(1988)

First nesting record of the Bay-Capped Wren-Spinetail Spartonoica maluroides (Aves, Furnariidae) in Brazil, with nest and nestling descriptions and notes on breeding behavior

The only breeding record of Spartonoica maluroides (d'Orbigny & Lafresnaye, 1837) for Brazil is based on the observation of a fledgling in southern Rio Grande do Sul in January 1976. On 7 December 2005 we discovered a nest containing three nestlings at the southeastern end of Lagoa Pequena, municipality of Pelotas, Rio Grande do Sul. The nest was concealed at the base of a cavity in a Spartina densiflora (Poaceae) tussock located at the edge of a saltmarsh. The nest was built of fine pieces of dead Scirpus olneyi (Cyperaceae) and S. densiflora leaves firmly interlaced to the internal leaves of the tussock. Live leaves of S. densiflora lining the cavity comprised a substantial part of the nest's architecture, forming most of its upper lateral walls and roof. The lower section was more elaborate, resembling a deep cup and forming a distinct incubation chamber. Adults reached the nest's interior through an irregular apical opening amidst the leaves. The nest was 244 mm high and 140 mm wide. The incubation chamber had an external diameter of 138.5 mm, an internal diameter of 79.4 mm and was 86 mm deep. It was lined with fine leaves and white plant fibers. Nestlings were five to six days old. A total of 107 neossoptiles restricted to the capital, spinal and alar tracts were recorded in one nestling. The distribution of neossoptiles in the ocular region of S. maluroides forms a distinct pattern which can be typical of Furnariidae and related families. Two adults attended the nest, bringing small insects to the nestlings and removing fecal sacs. We recorded at least 74 visits to the nest during a ca. 6 h period during an afternoon. The average number of visits per hour was 12.8 ± 1.3. An adult bird spent on average 0.7 ± 0.56 minutes inside the nest attending nestlings. The nest remained unattended on average for 3.61 ± 3.13 minutes. The hour of the day had no influence on the amount of time spent by an adult in the nest or away from it. We returned to the area on 15 December 2005 and found the nest abandoned. Observations confirm that S. maluroides is a resident breeder in southern Brazil and that the saltmarshes of the Lagoa do Patos estuary are an important year-round habitat for the species. A nestling and the nest were collected to document the record.

Deep sea fishes from the Gulf of Mexico, with the description of a new species, Squalogadus intermedius (Macrouroididae)

v.39:no.29(1959)

Space-time variation of the relative abundance of Limnoperna fortunei in deep zones of São Gonçalo Channel, Rio Grande do Sul, Brazil

This work describes the spatial-temporal variation of the relative abundance and size of Limnoperna fortunei (Dunker, 1857) collected in São Gonçalo Channel through bottom trawl with a 0.5 cm mesh, at depths between 3 and 6 m. The estimative of mean relative abundance (CPUE) ranged from 2,425.3 individuals per drag (ind./drag) in the spring to 21,715.0 ind./drag in the fall, with an average of 9,515.3 ind./drag throughout the year. The estimated mean density of L. fortunei for the deep region of São Gonçalo Channel ranged from 1.2 to 10.3 ind./m², and it was recorded a maximum density of 84.9 ind./m² in the fall of 2008. The method of sampling using bottom trawl enabled the capture of L. fortunei under the soft muddy bottom of the channel, in different sizes ranging from 0.4 to 3.2 cm. This shows that the structure of the L. fortunei adult population under the bottom of the São Gonçalo Channel is composed mostly of small individuals (<1.4 cm), which represent up to 74% of the population collected.

RADIC II: a fault tolerant architecture with flexible dynamic redundancy

The demand for computational power has been leading the improvement of the High Performance Computing (HPC) area, generally represented by the use of distributed systems like clusters of computers running parallel applications. In this area, fault tolerance plays an important role in order to provide high availability isolating the application from the faults effects. Performance and availability form an undissociable binomial for some kind of applications. Therefore, the fault tolerant solutions must take into consideration these two constraints when it has been designed. In this dissertation, we present a few side-effects that some fault tolerant solutions may presents when recovering a failed process. These effects may causes degradation of the system, affecting mainly the overall performance and availability. We introduce RADIC-II, a fault tolerant architecture for message passing based on RADIC (Redundant Array of Distributed Independent Fault Tolerance Controllers) architecture. RADIC-II keeps as maximum as possible the RADIC features of transparency, decentralization, flexibility and scalability, incorporating a flexible dynamic redundancy feature, allowing to mitigate or to avoid some recovery side-effects.