Dynamic programming solutions for decentralized state-feedback LQG problems with communication delays

This paper presents explicit solutions for a class of decentralized LQG problems in which players communicate their states with delays. A method for decomposing the Bellman equation into a hierarchy of independent subproblems is introduced. Using this decomposition, all of the gains for the optimal controller are computed from the solution of a single algebraic Riccati equation. © 2012 AACC American Automatic Control Council).

Developing ISO 14649-based conversational programming system for multi-channel complex machine tools

A multi-channel complex machine tool (MCCM) is a versatile machining system equipped with more than two spindles and turrets for both turning and milling operations. Despite the potential of such a tool, the value of the hardware is largely dependent on how the machine tools are effectively programmed for machining. In this paper we consider a shop-floor programming system based on ISO 14649 (called e-CAM), the international standard for the interface between computer-aided manufacture (CAM) and computer numerical control (CNC). To be deployed in practical industrial usage a great deal of research has to be carried out. In this paper we present: 1) Design consideration for an e-CAM system, 2) The architecture design of e-CAM, 3) Major algorithms to fulfill the modules defined in the architecture, and 4) Implementation details.

Packing LUT clusters with network flow programming

This paper describes a two-step packing algorithm for LUT clusters of which the LUT input multipliers are depopulated. In the first step, a greedy algorithm is used to search for BLE locations and cluster inputs. If the greedy algorithm fails, the second step with network flow programming algorithm is employed. Numerical results illustrate that our two-step packing algorithm obtains better packing density than one-step greedy packing algorithm.

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.