A 660MHz ZVS DC-DC converter using gate-driver charge-recycling in 0.18μm CMOS with an integrated output filter

The design and manufacture of a prototype chip level power supply is described, with both simulated and experimental results. Of particular interest is the inclusion of a fully integrated on-chip LC filter. A high switching frequency of 660MHz and the design of a device drive circuit reduce losses by supply stacking, low-swing signaling and charge recycling. The paper demonstrates that a chip level converter operating at high frequency can be built and shows how this can be achieved, using zero voltage switching techniques similar to those commonly used in larger converters. Both simulations and experimental data from a fabricated circuit in 0.18μm CMOS are included. The circuit converts 2.2V to 0.75∼1.0V at ∼55mA. ©2008 IEEE.

Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

Trench insulated gate bipolar transistor - a high power switching device

This paper presents a comprehensive theoretical study of the Trench Insulated Gate Bipolar Transistors (TIGBT). Specific physical and geometrical effects, such as the accumulation layer injection, increased channel density, increased channel charge and transversal electric field modulation are discussed. The potential advantages of the Trench IGBT over its conventional planar variant are highlighted. It is concluded that the Trench IGBT is one of the most promising structures in the area of high voltage MOS-controllable switching devices.

Dual gate photo-thin film transistor with high photoconductive gain for high reliability, and low noise flat panel transparent imager

In this presentation, we report excellent electrical and optical characteristics of a dual gate photo thin film transistor (TFT) with bi-layer oxide channel, which was designed to provide virgin threshold voltage (V T) control, improve the negative bias illumination temperature stress (NBITS) reliability, and offer high photoconductive gain. In order to address the photo-sensitivity of phototransistor for the incoming light, top transparent InZnO (IZO) gate was employed, which enables the independent gate control of dual gate photo-TFT without having any degradation of its photosensitivity. Considering optimum initial V T and NBITS reliability for the device operation, the top gate bias was judiciously chosen. In addition, the speed and noise performance of the photo-TFT is competitive with silicon photo-transistors, and more importantly, its superiority lies in optical transparency. © 2011 IEEE.

Cryogenic single-shot spectroscopy of a floating poly-silicon gate transistor

Trapped electrons, located close to the channel of a transistor, are promising as data storage elements in non-classical information processing. Cryogenic microwave spectroscopy has shown that these electrons give rise to high quality factor resonances in the drain current and a post excitation dynamic behaviour that is related to the system lifetime. Using a floating poly-silicon gate transistor, single shot spectroscopy is performed to characterise the dynamic behaviour during excitation. This behaviour is seen to be dominated by the decay of the transient component, which gives rise to oscillations around the high quality factor resonance. © 2012 American Institute of Physics.

Point injection in trench insulated gate bipolar transistor for ultra low losses

In this paper we propose novel designs that enhance the plasma concentration across the Field Stop IGBT. The "p-ring" and the "point-injection" type devices exhibit increased cathode side conductivity modulation which results in impressive IGBT performance improvement. These designs are shown to be extremely effective in lowering the on-state losses without compromising the switching performance or the breakdown rating. For the same switching losses we can achieve more than 20% reduction of the on state energy losses compared to the conventional FS IGBT. © 2012 IEEE.

Indirect modulation of a terahertz quantum cascade laser using gate tunable graphene

We bring together two areas of terahertz (THz) technology that have benefited from recent advancements in research, i.e., graphene, a material that has plasmonic resonances in the THz frequency, and quantum cascade lasers (QCLs), a compact electrically driven unipolar source of THz radiation. We demonstrate the use of single-layer large-area graphene to indirectly modulate a THz QCL operating at 2.0 THz. By tuning the Fermi level of the graphene via a capacitively coupled backgate voltage, the optical conductivity and, hence, the THz transmission can be varied. We show that, by changing the pulsing frequency of the backgate, the THz transmission can be altered. We also show that, by varying the pulsing frequency of the backgate from tens of Hz to a few kHz, the amplitude-modulated THz signal can be switched by 15% from a low state to a high state. © 2009-2012 IEEE.

Dead-time minimisation using active voltage control gate drive for high-power IGBT converters

High-power converters usually need longer dead-times than their lower-power counterparts and a lower switching frequency. Also due to the complicated assembly layout and severe variations in parasitics, in practice the conventional dead-time specific adjustment or compensation for high-power converters is less effective, and usually this process is time-consuming and bespoke. For general applications, minimising or eliminating dead-time in the gate drive technology is a desirable solution. With the growing acceptance of power electronics building blocks (PEBB) and intelligent power modules (IPM), gate drives with intelligent functions are in demand. Smart functions including dead time elimination/minimisation can improve modularity, flexibility and reliability. In this paper, a dead-time minimisation using Active Voltage Control (AVC) gate drive is presented. © 2012 IEEE.

Three-dimensional distribution of Al in high-k metal gate: Impact on transistor voltage threshold

The three-dimensional spatial distribution of Al in the high-k metal gates of metal-oxide-semiconductor field-effect-transistors is measured by atom probe tomography. Chemical distribution is correlated with the transistor voltage threshold (VTH) shift generated by the introduction of a metallic Al layer in the metal gate. After a 1050 °C annealing, it is shown that a 2-Å thick Al layer completely diffuses into oxide layers, while a positive VTH shift is measured. On the contrary, for thicker Al layers, Al precipitation in the metal gate stack is observed and the VTH shift becomes negative. © 2012 American Institute of Physics.

Three dimensional distributions of arsenic and platinum within NiSi contact and gate of an n-type transistor

Atom probe tomography was used to study the redistribution of platinum and arsenic atoms after Ni(Pt) silicidation of As-doped polycrystalline Si. These measurements were performed on a field-effect transistor and compared with those obtained in unpatterned region submitted to the same process. These results suggest that Pt and As redistribution during silicide formation is only marginally influenced by the confinement in microelectronic devices. On the contrary, there is a clear difference with the redistribution reported in the literature for the blanket wafers. Selective etching used to remove the non-reacted Ni(Pt) film after the first rapid heat treatment may induce this difference. © 2011 American Institute of Physics.

Polymer gate dielectrics with self-assembled monolayers for high-mobility organic thin-film transistors based on copper phthalocyanine

Organic thin-film transistors based on polycrystalline copper phthalocyanine (CuPc) were fabricated by using poly(vinyl alcohol) as gate dielectric. After treatment of the gate dielectric using an octadecyltrichlorosilane self-assembled monolayer, a mobility of up to 0.11 cm2/V∈s was achieved, which is comparable to that of single-crystal CuPc devices (0.1-1 cm2/V∈s). The surface morphology was analyzed and the possible reasons for the enhanced mobility are discussed. © 2009 Springer-Verlag.

200 v superjunction N-type lateral insulated-gate bipolar transistor with improved latch-up characteristics

This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong pnp transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (VON) of 2 V at 300 Acm2. The latch-up current density is 1100 Acm2. The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in VON. The latest design shows a latch-up current density of 1195 A cm2. The enhanced robustness against static latch-up leads to a better forward bias safe operating area. © 1963-2012 IEEE.