System-on-a-Chip (SoC) based hardware acceleration in Register Transfer Level (RTL) design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

Protótipo de rastreador solar de um eixo baseado em microcontrolador

The increase in the efficiency of photo-voltaic systems has been the object of various studies the past few years. One possible way to increase the power extracted by a photovoltaic panel is the solar tracking, performing its movement in order to follow the sun’s path. One way to activate the tracking system is using an electric induction motor, which should have sufficient torque and low speed, ensuring tracking accuracy. With the use of voltage source inverters and logic devices that generate the appropriate switching is possible to obtain the torque and speed required for the system to operate. This paper proposes the implementation of a angular position sensor and a driver to be applied in solar tracker built at a Power Electronics and Renewable Energies Laboratory, located in UFRN. The speed variation of the motor is performed via a voltage source inverter whose PWM command to actuate their keys will be implemented in an FPGA (Field Programmable Gate Array) device and a TM4C microcontroller. A platform test with an AC induction machine of 1.5 CV was assembled for the comparative testing. The angular position sensor of the panel is implemented in a ATMega328 microcontroller coupled to an accelerometer, commanded by an Arduino prototyping board. The solar position is also calculated by the microcontroller from the geographic coordinates of the site where it was placed, and the local time and date obtained from an RTC (Real-Time Clock) device. A prototype of a solar tracker polar axis moved by a DC motor was assembled to certify the operation of the sensor and to check the tracking efficiency.

Controllo ultra-low power di un modulatore back-scattering per applicazioni di localizzazione in sistemi RFID

In questa tesi viene elaborata un'applicazione ultra-low power (ULP) basata su microcontrollore, per implementare la procedura di controllo di diversi circuiti di un tag RFID. Il tag preso in considerazione è pensato per lavorare in assenza di batteria, da cui la necessita' di ridurre i consumi di potenza. La sua attivazione deve essere inoltre comandata attraverso un'architettura Wake up Radio (WuR), in cui un segnale di controllo radio indirizza e attiva il circuito. Nello specifico, la rete di decodifica dell'indirizzo è stata realizzata mediante il modulo di comunicazione seriale del microcontrollore. Nel Capitolo 1 verrà introdotto il tema dell'Energy Harvesting. Nel Capitolo 2 verrà illustrata l'architettura del sistema nel suo complesso. Nel Capitolo 3 verrà spiegato dettagliatamente il funzionamento del microcontrollore scelto. Il Capitolo 4 sarà dedicato al firmware implementato per svolgere le operazioni fondamentali imputate al micro per i compiti di controllo. Verrà inoltre introdotto il codice VHDL sviluppato per emulare l'output del modulo WuR mediante un FPGA della famiglia Cyclone II. Nel Capitolo 5 verrà presentata una stima dei consumi del microcontrollore in funzione dei parametri di configurazione del sistema. Verrà inoltre effettuato un confronto con un altro microcontrollore che in alcune condizioni potrebbe rappresentare iun'alternativa valida di progetto. Nei Capitoli 6 e 7 saranno descritti possibili sviluppi futuri e conclusioni del progetto. Le specifiche di progetto rilevanti della tesi sono: 1. minimo consumo energetico possibile del microcontrollore ULP 2. elevata rapidità di risposta per la ricezione dei tag, per garantire la ricezione di un numero maggiore possibile di indirizzi (almeno 20 letture al secondo), in un range di tempo limitato 3. generazione di un segnale PWM a 100KHz di frequenza di commutazione con duty cycle 50% su cui basare una modulazione in back-scattering.

Análise da força propulsora do motor de indução linear alimentado com imposição de corrente

This work intent to study the motive power provided by the plane linear induction motor, in a lock condition. It uses a method of imposition of the electric current to the stator via a frequency convertor PWM driven by a refed platform. The reading of the motive power was performed by a load cell using an electronic circuit for reading and conditioning of the signal. Aiming a complete analysis of the linear motor, it was performed a computational modeling that employs all relevant parameters to the study of the locked machine. At the end it was held a theoric-experimental confrontation that evaluated the effectiveness of the proposed method.

Constant V/Hz control based on DSP for open winding doubly-fed wind power generator

A DSP implementation of Space Vector PWM (SVPWM) using constant V/Hz control for the open winding doubly-fed generator is proposed. This control of SVPWM modulation mode and open winding structure combination has the high voltage utilization ratio, greatly improves the control precision of the system, and reduces the stator winding output current distortion rate, though the complexity of the system is increased. This paper describes the basic principle of SVPWM and discusses the particularity of SVPWM waveform generated by hybrid vector under the condition of open winding. This method is applied to a state of doubly-fed wind power generator. The experimental verification shows that this control method can make the output voltage amplitude of the doubly-fed induction generator be 380V and the frequency be 50Hz by using of TMS32028335 chip based on constant V/Hz control of symmetric SVPWM modulation wave.

Calcium/Calmodulin-Dependent Protein Kinase II Serves as a Biochemical Integrator of Calcium Signals for the Induction of Synaptic Plasticity

Repetitive Ca2+ transients in dendritic spines induce various forms of synaptic plasticity by transmitting information encoded in their frequency and amplitude. CaMKII plays a critical role in decoding these Ca2+ signals to initiate long-lasting synaptic plasticity. However, the properties of CaMKII that mediate Ca2+ decoding in spines remain elusive. Here, I measured CaMKII activity in spines using fast-framing two-photon fluorescence lifetime imaging. Following each repetitive Ca2+ elevations, CaMKII activity increased in a stepwise manner. This signal integration, at the time scale of seconds, critically depended on Thr286 phosphorylation. In the absence of Thr286 phosphorylation, only by increasing the frequency of repetitive Ca2+ elevations could high peak CaMKII activity or plasticity be induced. In addition, I measured the association between CaMKII and Ca2+/CaM during spine plasticity induction. Unlike CaMKII activity, association of Ca2+/CaM to CaMKII plateaued at the first Ca2+ elevation event. This result indicated that integration of Ca2+ signals was initiated by the binding of Ca2+/CaM and amplified by the subsequent increases in Thr286-phosphorylated form of CaMKII. Together, these findings demonstrate that CaMKII functions as a leaky integrator of repetitive Ca2+ signals during the induction of synaptic plasticity, and that Thr286 phosphorylation is critical for defining the frequencies of such integration.

Saccharomycotin transcriptomics by next-generation sequencing

The non-standard decoding of the CUG codon in Candida cylindracea raises a number of questions about the evolutionary process of this organism and other species Candida clade for which the codon is ambiguous. In order to find some answers we studied the transcriptome of C. cylindracea, comparing its behavior with that of Saccharomyces cerevisiae (standard decoder) and Candida albicans (ambiguous decoder). The transcriptome characterization was performed using RNA-seq. This approach has several advantages over microarrays and its application is booming. TopHat and Cufflinks were the software used to build the protocol that allowed for gene quantification. About 95% of the reads were mapped on the genome. 3693 genes were analyzed, of which 1338 had a non-standard start codon (TTG/CTG) and the percentage of expressed genes was 99.4%. Most genes have intermediate levels of expression, some have little or no expression and a minority is highly expressed. The distribution profile of the CUG between the three species is different, but it can be significantly associated to gene expression levels: genes with fewer CUGs are the most highly expressed. However, CUG content is not related to the conservation level: more and less conserved genes have, on average, an equal number of CUGs. The most conserved genes are the most expressed. The lipase genes corroborate the results obtained for most genes of C. cylindracea since they are very rich in CUGs and nothing conserved. The reduced amount of CUG codons that was observed in highly expressed genes may be due, possibly, to an insufficient number of tRNA genes to cope with more CUGs without compromising translational efficiency. From the enrichment analysis, it was confirmed that the most conserved genes are associated with basic functions such as translation, pathogenesis and metabolism. From this set, genes with more or less CUGs seem to have different functions. The key issues on the evolutionary phenomenon remain unclear. However, the results are consistent with previous observations and shows a variety of conclusions that in future analyzes should be taken into consideration, since it was the first time that such a study was conducted.

'Enhanced Direct and Indirect Genetic Algorithm Approaches for a Mall Layout and Tenant Selection Problem'

During our earlier research, it was recognised that in order to be successful with an indirect genetic algorithm approach using a decoder, the decoder has to strike a balance between being an optimiser in its own right and finding feasible solutions. Previously this balance was achieved manually. Here we extend this by presenting an automated approach where the genetic algorithm itself, simultaneously to solving the problem, sets weights to balance the components out. Subsequently we were able to solve a complex and non-linear scheduling problem better than with a standard direct genetic algorithm implementation.

Sistema de armazenamento de energia com base em baterias e no ondulador de tensão trifásico

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica Ramo de Automação e Eletrotécnica Ramo de Automação e Eletrónica Industrial

An Indirect Genetic Algorithm for Set Covering Problems

This paper presents a new type of genetic algorithm for the set covering problem. It differs from previous evolutionary approaches first because it is an indirect algorithm, i.e. the actual solutions are found by an external decoder function. The genetic algorithm itself provides this decoder with permutations of the solution variables and other parameters. Second, it will be shown that results can be further improved by adding another indirect optimisation layer. The decoder will not directly seek out low cost solutions but instead aims for good exploitable solutions. These are then post optimised by another hill-climbing algorithm. Although seemingly more complicated, we will show that this three-stage approach has advantages in terms of solution quality, speed and adaptability to new types of problems over more direct approaches. Extensive computational results are presented and compared to the latest evolutionary and other heuristic approaches to the same data instances.

A New Genetic Algorithm for Set Covering Problems

An indirect genetic algorithm for the non-unicost set covering problem is presented. The algorithm is a two-stage meta-heuristic, which in the past was successfully applied to similar multiple-choice optimisation problems. The two stages of the algorithm are an ‘indirect’ genetic algorithm and a decoder routine. First, the solutions to the problem are encoded as permutations of the rows to be covered, which are subsequently ordered by the genetic algorithm. Fitness assignment is handled by the decoder, which transforms the permutations into actual solutions to the set covering problem. This is done by exploiting both problem structure and problem specific information. However, flexibility is retained by a self-adjusting element within the decoder, which allows adjustments to both the data and to stages within the search process. Computational results are presented.

Enhanced Direct and Indirect Genetic Algorithm Approaches for a Mall Layout and Tenant Selection Problem

During our earlier research, it was recognised that in order to be successful with an indirect genetic algorithm approach using a decoder, the decoder has to strike a balance between being an optimiser in its own right and finding feasible solutions. Previously this balance was achieved manually. Here we extend this by presenting an automated approach where the genetic algorithm itself, simultaneously to solving the problem, sets weights to balance the components out. Subsequently we were able to solve a complex and non-linear scheduling problem better than with a standard direct genetic algorithm implementation.

Arquitetura híbrida com DSP e FPGA para implementação de controladores de filtros ativos de potência

The presence of non-linear loads at a point in the distribution system may deform voltage waveform due to the consumption of non-sinusoidal currents. The use of active power filters allows significant reduction of the harmonic content in the supply current. However, the processing of digital control structures for these filters may require high performance hardware, particularly for reference currents calculation. This work describes the development of hardware structures with high processing capability for application in active power filters. In this sense, it considers an architecture that allows parallel processing using programmable logic devices. The developed structure uses a hybrid model using a DSP and an FPGA. The DSP is used for the acquisition of current and voltage signals, calculation of fundamental current related controllers and PWM generation. The FPGA is used for intensive signal processing, such as the harmonic compensators. In this way, from the experimental analysis, significant reductions of the processing time are achieved when compared to traditional approaches using only DSP. The experimental results validate the designed structure and these results are compared with other ones from architectures reported in the literature.

An Indirect Genetic Algorithm for a Nurse Scheduling Problem

This paper describes a Genetic Algorithms approach to a manpower-scheduling problem arising at a major UK hospital. Although Genetic Algorithms have been successfully used for similar problems in the past, they always had to overcome the limitations of the classical Genetic Algorithms paradigm in handling the conflict between objectives and constraints. The approach taken here is to use an indirect coding based on permutations of the nurses, and a heuristic decoder that builds schedules from these permutations. Computational experiments based on 52 weeks of live data are used to evaluate three different decoders with varying levels of intelligence, and four well-known crossover operators. Results are further enhanced by introducing a hybrid crossover operator and by making use of simple bounds to reduce the size of the solution space. The results reveal that the proposed algorithm is able to find high quality solutions and is both faster and more flexible than a recently published Tabu Search approach.

'An Indirect Genetic Algorithm for Set Covering Problems'

This paper presents a new type of genetic algorithm for the set covering problem. It differs from previous evolutionary approaches first because it is an indirect algorithm, i.e. the actual solutions are found by an external decoder function. The genetic algorithm itself provides this decoder with permutations of the solution variables and other parameters. Second, it will be shown that results can be further improved by adding another indirect optimisation layer. The decoder will not directly seek out low cost solutions but instead aims for good exploitable solutions. These are then post optimised by another hill-climbing algorithm. Although seemingly more complicated, we will show that this three-stage approach has advantages in terms of solution quality, speed and adaptability to new types of problems over more direct approaches. Extensive computational results are presented and compared to the latest evolutionary and other heuristic approaches to the same data instances.