Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence scheme

Exploiting the performance potential of GPUs requires managing the data transfers to and from them efficiently which is an error-prone and tedious task. In this paper, we develop a software coherence mechanism to fully automate all data transfers between the CPU and GPU without any assistance from the programmer. Our mechanism uses compiler analysis to identify potential stale accesses and uses a runtime to initiate transfers as necessary. This allows us to avoid redundant transfers that are exhibited by all other existing automatic memory management proposals. We integrate our automatic memory manager into the X10 compiler and runtime, and find that it not only results in smaller and simpler programs, but also eliminates redundant memory transfers. Tested on eight programs ported from the Rodinia benchmark suite it achieves (i) a 1.06x speedup over hand-tuned manual memory management, and (ii) a 1.29x speedup over another recently proposed compiler--runtime automatic memory management system. Compared to other existing runtime-only and compiler-only proposals, it also transfers 2.2x to 13.3x less data on average.

Joint Evaluation of Reduced Feedback Scheme, Scheduling, and Rate Adaptation in OFDMA Systems with Feedback Delays

Orthogonal frequency division multiple access (OFDMA) systems exploit multiuser diversity and frequency-selectivity to achieve high spectral efficiencies. However, they require considerable feedback for scheduling and rate adaptation, and are sensitive to feedback delays. We develop a comprehensive analysis of the OFDMA system throughput as a function of the feedback scheme, frequency-domain scheduler, and discrete rate adaptation rule in the presence of feedback delays. We analyze the popular best-n and threshold-based feedback schemes. We show that for both the greedy and round-robin schedulers, the throughput degradation, given a feedback delay, depends primarily on the fraction of feedback reduced by the feedback scheme and not the feedback scheme itself. Even small feedback delays at low vehicular speeds are shown to significantly degrade the throughput. We also show that optimizing the link adaptation thresholds as a function of the feedback delay can effectively counteract the detrimental effect of delays.

Group testing based spectrum hole search using a simple sub-nyquist sampling scheme

In this paper, we consider the problem of finding a spectrum hole of a specified bandwidth in a given wide band of interest. We propose a new, simple and easily implementable sub-Nyquist sampling scheme for signal acquisition and a spectrum hole search algorithm that exploits sparsity in the primary spectral occupancy in the frequency domain by testing a group of adjacent subbands in a single test. The sampling scheme deliberately introduces aliasing during signal acquisition, resulting in a signal that is the sum of signals from adjacent sub-bands. Energy-based hypothesis tests are used to provide an occupancy decision over the group of subbands, and this forms the basis of the proposed algorithm to find contiguous spectrum holes. We extend this framework to a multi-stage sensing algorithm that can be employed in a variety of spectrum sensing scenarios, including non-contiguous spectrum hole search. Further, we provide the analytical means to optimize the hypothesis tests with respect to the detection thresholds, number of samples and group size to minimize the detection delay under a given error rate constraint. Depending on the sparsity and SNR, the proposed algorithms can lead to significantly lower detection delays compared to a conventional bin-by-bin energy detection scheme; the latter is in fact a special case of the group test when the group size is set to 1. We validate our analytical results via Monte Carlo simulations.

An adaptive modulation scheme for two-user fading MAC with quantized fade state feedback

For transmission over the two-user Gaussian Multiple Access Channel with fading and finite constellation at the inputs, we propose a scheme which uses only quantized knowledge of fade state at users with the feedback overhead being nominal. One of the users rotates its constellation without varying the transmit power to adapt to the existing channel conditions, in order to meet certain pre-determined minimum Euclidean distance requirement in the equivalent constellation at the destination. The optimal modulation scheme has been described for the case when both the users use symmetric M-PSK constellations at the input, where M = 2λ, λ being a positive integer. The strategy has been illustrated by considering examples where both the users use QPSK signal set at the input. It is shown that the proposed scheme has considerable better error performance compared to the conventional non-adaptive scheme, at the cost of a feedback overhead of just [log2 (M2/8 - M/4 + 2)] + 1 bits, for the M-PSK case.

A Cooperative ARQ Scheme for Infrastructure WLANs

We propose a Cooperative Opportunistic Automatic Repeat ReQuest (CoARQ) scheme to solve the HOL-blocking problem in infrastructure IEEE 802.11 WLANs. HOL blocking occurs when the head-of-the-line packet at the Access Point (AP) queue blocks the transmission of packets to other destinations resulting in severe throughput degradation. When the AP transmits a packet to a mobile station (STA), some of the nodes in the vicinity can overhear this packet transmission successfully. If the original transmission by the AP is unsuccessful, our CoARQ scheme chooses the station. STA or AP) with the best channel to the intended receiver as a relay and the chosen relay forwards the AP's packet to the receiver. This way, our scheme removes the bottleneck at the AP, thereby providing significant improvements in the throughput of the AP. We analyse the performance of our scheme in an infrastructure WLAN under a TCP controlled file download scenario and our analytical results are further validated by extensive simulations.

Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance

In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experimentally. The phenomenon of noise coupling to the PLL is also explained through experiments. The PLL output frequency is 500 MHz and it is implemented in the 0.13-mu m CMOS technology. Measurements show a reduction of 12.53 dB in the PLL output spur level at an offset of 5 MHz and a reduction of 107 ps in the Pk-Pk deterministic period jitter upon reducing the duty cycle of the signal injected into the substrate from 50% to 20%. The results of the analyses suggest that using a pulsed clocking scheme for digital systems in mixed-signal integration along with other isolation techniques helps reduce the substrate noise effects on sensitive analog/radio-frequency circuits.

Implementation of throughput enhancing client-AP association scheme On a WLAN controller

In a typical enterprise WLAN, a station has a choice of multiple access points to associate with. The default association policy is based on metrics such as Re-ceived Signal Strength(RSS), and “link quality” to choose a particular access point among many. Such an approach can lead to unequal load sharing and diminished system performance. We consider the RAT (Rate And Throughput) policy [1] which leads to better system performance. The RAT policy has been implemented on home-grown centralized WLAN controller, ADWISER [2] and we demonstrate that the RAT policy indeed provides a better system performance.

A 5th and 7th Order Harmonic Suppression Scheme for Open-end Winding Asymmetrical Six-phase IM Drive Using Capacitor-fed Inverter

Voltage source inverter (VSI) fed six-phase induction motor drives have high 6n +/- 1; n = odd order harmonic currents, due to absence of back emf for these currents. To suppress these harmonic currents, either bulky inductive harmonic filters or complex pulse width modulation (PWM) techniques have to be used. This paper proposes a simple harmonic elimination scheme using capacitor fed inverters, for an asymmetrical six-phase induction motor VSI fed drive. Two three phase inverters fed from a single capacitor is used on the open-end side of the motor, to suppress 6n +/- 1; n = odd order harmonics. A PWM scheme that can suppress the harmonics, as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected. The proposed scheme is verified using MATLAB Simulink simulation at different speeds. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters. Experimental results are also provided to validate the functionality of the proposed controller.

A Harmonic Suppression Scheme for Open-End Winding Split-Phase IM Drive Using Capacitive Filters for the Full Speed Range

Voltage source inverter (VSI)-fed six-phase induction motor (IM) drives have high 6n +/- 1, n = odd-order harmonic currents. This is because these currents, driven by the corresponding harmonic voltages in the inverter output, are limited only by the stator leakage impedance, as these harmonics are absent in the back electromotive force of the motor. To suppress the harmonic currents, either bulky inductive harmonic filters or complex pulsewidth modulation (PWM) techniques have to be used. This paper proposes a harmonic elimination scheme using switched capacitor filters for a VSI-fed split-phase IM drive. Two 3-phase inverters fed from capacitors are used on the open-end side of the motor to suppress 6n +/- 1, n = odd-order harmonics. A PWM scheme that can suppress the harmonics as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected, and the fundamental power is always drawn from the main inverters. The proposed scheme is verified with a detailed experimental study. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters.

Design of fully rotatable, roller-crank-driven, cam mechanisms for arbitrary motion specifications

The design of a non-traditional cam and roller-follower mechanism is described here. In this mechanism, the roller-crank rather than the cam is used as the continuous input member, while both complete a full rotation in each revolution and remain in contact throughout. It is noted that in order to have the cam fully rotate for every full rotation of the roller-crank, the cam cannot be a closed profile, rather the roller traverses the open cam profile twice in each cycle. Using kinematic analysis, the angular velocity of the cam when the roller traverses the cam profile in one direction, is related to the angular velocity of the cam when the roller retraces its path on the cam in the other direction. Thus, one can specify any arbitrary function relating the motion of the cam to the motion of the roller-crank for only 180 degrees of rotation in the angular velocity space. The motion of the cam in the remaining portion is then automatically determined. In specifying the arbitrary motion, many desirable characteristics such as multiple dwells, low acceleration and jerk, etc., can be obtained. Useful design equations are derived for this purpose. Using the kinematic inversion technique, the cam profile is readily obtained once the motion is specified in the angular velocity space. The only limitation to the arbitrary motion specification is making sure that the transmission angle never gets too low, so that the force will be transmitted efficiently from roller to cam. This is addressed by incorporating a transmission index into the motion specification in the synthesis process. Consequently, in this method we can specify any arbitrary motion within a permissible rone, such that the transmission index is higher than the specified minimum value. Single-dwell, double-dwell and a long hesitation motion are used as examples to demonstrate the ffectiveness of the design method. Force closure using an optimally located spring and quasi-kinetostatic analysis are also discussed. (C) 2001 Elsevier Science Ltd. All rights reserved.

Space vector based modulation scheme for reducing capacitor RMS current in three-level diode-clamped inverter

The DC capacitor is an important component in a voltage source inverter.The RMS current flowing through the capacitor determines the capacitor size and losses. The losses, in turn, influence the capacitor life. This paper proposes a space vector based modulation strategy for reducing the capacitor RMS current in a three-level diode-clamped inverter. An analytical closed-form expression is derived for the DC capacitor RMS current with the proposed PWM strategy. The analytical expression is validated through simulations and also experimentally. Theoretical and experimental results are presented, comparing the proposed strategy with conventional space vector PWM (CSVPWM). It is shown that the proposed strategy reduces the capacitor RMS current significantly at high modulation indices and high power factors. (C) 2014 Elsevier B.V. All rights reserved.

An Improved Dead-Time Compensation Scheme for Voltage Source Inverters Considering the Device Switching Transition Times

Inverter dead-time, which is meant to prevent shoot-through fault, causes harmonic distortion and change in the fundamental voltage in the inverter output. Typical dead-time compensation schemes ensure that the amplitude of the fundamental output current is as desired, and also improve the current waveform quality significantly. However, even with compensation, the motor line current waveform is observed to be distorted close to the current zero-crossings. The IGBT switching transition times being significantly longer at low currents than at high currents is an important reason for this zero-crossover distortion. Hence, this paper proposes an improved dead-time compensation scheme, which makes use of the measured IGBT switching transition times at low currents. Measured line current waveforms in a 2.2 kW induction motor drive with the proposed compensation scheme are compared against those with the conventional dead-time compensation scheme and without dead-time compensation. The experimental results on the motor drive clearly demonstrate the improvement in the line current waveform quality with the proposed method.

A 5th and 7th order harmonic suppression scheme using capacitive filtering for 2-level VSI fed IM drive

In this paper, a 5th and 7th harmonic suppression technique for a 2-level VSI fed IM drive, by using capacitive filtering is proposed. A capacitor fed 2-level inverter is used on an open-end winding induction motor to suppress all 5th and 7th order harmonics. A PWM scheme that maintains the capacitor voltage, while suppressing the harmonics is also proposed. The proposed scheme is valid for the entire modulation range, including overmodulation and six-step mode of operation of the main inverter.

Boundary Tracking using a Hybrid Cyclic Pursuit Scheme

There has been a lot of work in the literature, related to the mapping of boundaries of regions, using multiple agents. Most of these are based on optimization techniques or rely on potential fields to drive the agents towards the boundary and then retain them there while they space out evenly along the perimeter or surface (in two-dimensional and three-dimensional cases, respectively). In this paper an algorithm to track the boundary of a region in space is provided based on the cyclic pursuit scheme. This enables the agents to constantly move along the perimeter in a cluster, thereby tracking a dynamically changing boundary. The trajectories of the agents provide a sketch of the boundary. The use of multiple agents may facilitate minimization of tracking error by providing accurate estimates of points on the boundary, besides providing redundancy. Simulation results are provided to highlight the performance of the proposed scheme.

Timer-Based Distributed Node Selection Scheme Exploiting Power Control and Capture

Opportunistic selection in multi-node wireless systems improves system performance by selecting the ``best'' node and by using it for data transmission. In these systems, each node has a real-valued local metric, which is a measure of its ability to improve system performance. Our goal is to identify the best node, which has the largest metric. We propose, analyze, and optimize a new distributed, yet simple, node selection scheme that combines the timer scheme with power control. In it, each node sets a timer and transmit power level as a function of its metric. The power control is designed such that the best node is captured even if. other nodes simultaneously transmit with it. We develop several structural properties about the optimal metric-to-timer-and-power mapping, which maximizes the probability of selecting the best node. These significantly reduce the computational complexity of finding the optimal mapping and yield valuable insights about it. We show that the proposed scheme is scalable and significantly outperforms the conventional timer scheme. We investigate the effect of. and the number of receive power levels. Furthermore, we find that the practical peak power constraint has a negligible impact on the performance of the scheme.