Active micromachined integrated terahertz circuits

Schottky barrier diodes have been integrated into on-chip rectangular waveguides. Two novel techniques have been developed to fabricate diodes with posts suitable for integration into waveguides. One technique produces diodes with anode diameters of the order of microns with post heights from 90 to 125 microns and the second technique produces sub-micron anodes with post heights around 20 microns. A method has been developed to incorporate these structures into a rectangular waveguide and provide a top contact onto the anode which could be used as an I.F. output in a mixer circuit. Devices have been fabricated and D.C. characterized.

Rap1-Rac1 circuits potentiate platelet activation.

OBJECTIVE: The goal of this study was to investigate the potential crosstalk between Rap1 and Rac1, 2 small GTPases central to platelet activation, particularly downstream of the collagen receptor GPVI. METHODS AND RESULTS: We compared the activation response of platelets with impaired Rap signaling (double knock-out; deficient in both the guanine nucleotide exchange factor, CalDAG-GEFI, and the Gi-coupled receptor for ADP, P2Y12), to that of wild-type platelets treated with a small-molecule Rac inhibitor, EHT 1864 (wild-type /EHT). We found that Rac1 is sequentially activated downstream of Rap1 on stimulation via GPVI. In return, Rac1 provides important feedback for both CalDAG-GEFI- and P2Y12-dependent activation of Rap1. When analyzing platelet responses controlled by Rac1, we observed (1) impaired lamellipodia formation, clot retraction, and granule release in both double knock-out and EHT 1864-treated wild-type platelets; and (2) reduced calcium store release in EHT 1864-treated wild-type but not double knock-out platelets. Consistent with the latter finding, we identified 2 pools of Rac1, one activated immediately downstream of GPVI and 1 activated downstream of Rap1. CONCLUSIONS: We demonstrate important crosstalk between Rap1 and Rac1 downstream of GPVI. Whereas Rap1 signaling directly controls sustained Rac1 activation, Rac1 affects CalDAG-GEFI- and P2Y12-dependent Rap1 activation via its role in calcium mobilization and granule/ADP release, respectively.

Neuronal Expression of Cd36, Cd44, and Cd83 Antigen Transcripts Maps to Distinct and Specific Murine Brain Circuits

Cells recruited by the innate immune response rely on surface-expressed molecules in order to receive signals from the local environment and to perform phagocytosis, cell adhesion, and others processes linked to host defense. Hundreds of surface antigens designated through a cluster of differentiation (CD) number have been used to identify particular populations of leukocytes. Surprisingly, we verified that the genes that encode Cd36 and Cd83 are constitutively expressed in specific neuronal cells. For instance, Cd36 mRNA is expressed in some regions related to circuitry involved in pheromone responses and reproductive behavior. Cd44 expression, reanalyzed and detailed here, is associated with the laminar formation and midline thalamic nuclei in addition to striatum, extended amygdala, and a few hypothalamic, cortical, and hippocampal regions. A systemic immune challenge was able to increase Cd44 expression quickly in the area postrema and motor nucleus of the vagus but not in regions presenting expressive constitutive expression. In contrast to Cd36 and Cd44, Cd83 message was widely distributed from the olfactory bulb to the brain stem reticular formation, sparing the striatopallidum, olivary region, and cerebellum. Its pattern of expression nevertheless remained strongly associated with hypothalamic, thalamic, and hindbrain nuclei. Unlike the other transcripts, Cd83 mRNA was rapidly modulated by restraint stress. Our results indicate that these molecules might play a role in specific neural circuits and present functions other than those attributed to leukocyte biology. The data also suggest that these surface proteins, or their associated mRNA, could be used to label neurons in specific circuits/regions. J. Comp. Neurol. 517:906-924, 2009. (C) 2009 Wiley-Liss, Inc.

Equivalent Circuits and Nanoplasmonics

We show how a circuit analysis, used widely in electrical engineering, finds application to problems of light wave injection and transport in subwavelength structures in the optical frequency range. Lumped circuit and transmission-line analysis may prove helpful in the design of plasmonic devices with standard, functional properties.

Claude Elwood Shannon e a symbolic analysis of relay and switching circuits: tornando o computador uma máquina semiótica.

O nome de Claude Elwood Shannon não é totalmente estranho aos pesquisadores de Comunicação Social. No entanto, parte de sua importância para a história da comunicação no século XX é pouco conhecida. Sua dissertação de mestrado e o artigo dela derivado (A Symbolic Analysis of Relay and Switching Circuits) foram essenciais para que o computador se tornasse uma máquina de comunicação e, conseqüentemente, penetrasse em nossa sociedade na forma como ocorre hoje. Este artigo revisa o primeiro grande trabalho de Shannon e explicita sua participação no contexto atual da comunicação.

Functional timing analysis of VLSI circuits containing complex gates

The recent advances in CMOS technology have allowed for the fabrication of transistors with submicronic dimensions, making possible the integration of tens of millions devices in a single chip that can be used to build very complex electronic systems. Such increase in complexity of designs has originated a need for more efficient verification tools that could incorporate more appropriate physical and computational models. Timing verification targets at determining whether the timing constraints imposed to the design may be satisfied or not. It can be performed by using circuit simulation or by timing analysis. Although simulation tends to furnish the most accurate estimates, it presents the drawback of being stimuli dependent. Hence, in order to ensure that the critical situation is taken into account, one must exercise all possible input patterns. Obviously, this is not possible to accomplish due to the high complexity of current designs. To circumvent this problem, designers must rely on timing analysis. Timing analysis is an input-independent verification approach that models each combinational block of a circuit as a direct acyclic graph, which is used to estimate the critical delay. First timing analysis tools used only the circuit topology information to estimate circuit delay, thus being referred to as topological timing analyzers. However, such method may result in too pessimistic delay estimates, since the longest paths in the graph may not be able to propagate a transition, that is, may be false. Functional timing analysis, in turn, considers not only circuit topology, but also the temporal and functional relations between circuit elements. Functional timing analysis tools may differ by three aspects: the set of sensitization conditions necessary to declare a path as sensitizable (i.e., the so-called path sensitization criterion), the number of paths simultaneously handled and the method used to determine whether sensitization conditions are satisfiable or not. Currently, the two most efficient approaches test the sensitizability of entire sets of paths at a time: one is based on automatic test pattern generation (ATPG) techniques and the other translates the timing analysis problem into a satisfiability (SAT) problem. Although timing analysis has been exhaustively studied in the last fifteen years, some specific topics have not received the required attention yet. One such topic is the applicability of functional timing analysis to circuits containing complex gates. This is the basic concern of this thesis. In addition, and as a necessary step to settle the scenario, a detailed and systematic study on functional timing analysis is also presented.

Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors

The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.

Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.