Compact CPW-fed uniplanar antenna for multiband wireless applications

A compact coplanar waveguide (CPW) fed uniplanar antenna for Quad-band applications is presented. The Quad-band operation is realized by imposing various current paths in a modified T-shaped radiating element. The antenna covers GSM 900, DCS 1800, IEEE802.11.a, IEEE802.11.b and HiperLAN-2 bands and exhibits good radiation characteristics. This low profile antenna has a dimension of 32mm×31mmwhen printed on a substrate of dielectric constant 4.4 and height 1.6mm. Details of design with experimental and simulated results are presented

CPW-Fed Quad-Band Antenna for Compact Wireless Application

This paper presents the design and development of a compact CPW fed quad band antenna. This low profile antenna has a dimension of 32mmx31mm when printed on a substrate of dielectric constant 4.4 and height 1.6mm. The antenna covers GSM 900, DCS 1800, IEEE802.11.a, IEEE802.11.b and HiperLAN2 bands. The antenna exhibits good radiation characteristics with moderate gain

Design of a Compact Genetic Microstrip Antenna with improved performance

In this paper the design issues of compact genetic microstrip antennas for mobile applications has been investigated. The antennas designed using Genetic Algorithms (GA) have an arbitrary shape and occupies less area (compact) compared to the traditionally designed antenna for the same frequency but with poor performance. An attempt has been made to improve the performance of the genetic microstrip antenna by optimizing the ground plane (GP) to have a fish bone like structure. The genetic antenna with the GP optimized is even better compared to the traditional and the genetic antenna.

Comments on Simple and Accurate Formula for the Resonant Frequency of the Equilateral Triangular Microstrip Patch Antenna

Antennas and Propagation, IEEE Transactions on,VOL 48,issue 4,pp 636

A Multi-Objective Antenna Placement Genetic Algorithm for Matched Array Synthesis on Complex Platforms

A Multi-Objective Antenna Placement Genetic Algorithm (MO-APGA) has been proposed for the synthesis of matched antenna arrays on complex platforms. The total number of antennas required, their position on the platform, location of loads, loading circuit parameters, decoupling and matching network topology, matching network parameters and feed network parameters are optimized simultaneously. The optimization goal was to provide a given minimum gain, specific gain discrimination between the main and back lobes and broadband performance. This algorithm is developed based on the non-dominated sorting genetic algorithm (NSGA-II) and Minimum Spanning Tree (MST) technique for producing diverse solutions when the number of objectives is increased beyond two. The proposed method is validated through the design of a wideband airborne SAR

Theoretical investigations of an annular elliptical ring microstrip antenna using Green‘s function technique

Analytical expressions for the Green’s function of an annular elliptical ring microstrip antenna (AERMA) are developed and reported. The modal, radiation and input impedance characteristics of the TM, modes are determined from these expressions. The resonant frequencies of odd modes are greater than that of the even modes for all TMnl modes (n = 1, 2, 3, ...) udke elliptical microstrip structures. The radiation pattern and input imedance curves of TMI2 mode on comparison with available experimental result shows good agreement whch provides an independent validation to this technique. The performance of the AERMA is then investigated as a function of thickness and substrate dielectric permittivity.

Reconfigurable Architectures for General-Purpose Computing

General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations. We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space. Our DPGA, a fine- grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite- state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds. Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today's silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20x the computational density of conventional processors. Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures.

Disseny d’un circuit analògic reconfigurable

En l’actualitat, l’electrònica digital s’està apoderant de la majoria de camps de desenvolupament, ja que ofereix un gran ventall de possibilitats que permeten fer front a gran quantitat de problemàtiques. Poc a Poc s’ha anat prescindint el màxim possible de l’electrònica analògica i en el seu lloc s’han utilitzat sistemes microprocessats, PLDs o qualsevol altre dispositiu digital, que proporciona beneficis enlluernadors davant la fatigosa tasca d’implementar una solució analògica. Tot i aquesta tendència, és inevitable la utilització de l’electrònica analògica, ja que el mon que ens envolta és l’entorn en el que han de proporcionar servei els diferents dissenys que es realitzen, i aquest entorn no és discret sinó continu. Partint d’aquest punt ben conegut hem de ser conscients que com a mínim els filtres d’entrada i sortida de senyal juntament amb els convertidors D/A A/D mai desapareixeran. Així doncs, aquests circuits analògics, de la mateixa forma que els digitals, han de ser comprovats un cop dissenyats, és en aquest apartat on el nostre projecte desenvoluparà un paper protagonista, ja que serà la eina que ha de permetre obtenir les diferents senyals característiques d’un determinat circuit, per posteriorment realitzar els tests que determinaran si es compleix el rang de correcte funcionament, i en cas de no complir, poder concretar quin paràmetre és el causant del defecte

A reconfigurable neural environment on active networks

This paper proposes the deployment of a neural network computing environment on Active Networks. Active Networks are packet-switched computer networks in which packets can contain code fragments that are executed on the intermediate nodes. This feature allows the injection of small pieces of codes to deal with computer network problems directly into the network core, and the adoption of new computing techniques to solve networking problems. The goal of our project is the adoption of a distributed neural network for approaching tasks which are specific of the computer network environment. Dynamically reconfigurable neural networks are spread on an experimental wide area backbone of active nodes (ABone) to show the feasibility of the proposed approach.

The systolic array genetic algorithm, an example of systolic arrays as a reconfigurable design methodology

We advocate the use of systolic design techniques to create custom hardware for Custom Computing Machines. We have developed a hardware genetic algorithm based on systolic arrays to illustrate the feasibility of the approach. The architecture is independent of the lengths of chromosomes used and can be scaled in size to accommodate different population sizes. An FPGA prototype design can process 16 million genes per second.

Detecting the number of signals using antenna array: a single threshold solution

A new approach is presented to identify the number of incoming signals in antenna array processing. The new method exploits the inherent properties existing in the noise eigenvalues of the covariance matrix of the array output. A single threshold has been established concerning information about the signal and noise strength, data length, and array size. When the subspace-based algorithms are adopted the computation cost of the signal number detector can almost be neglected. The performance of the threshold is robust against low SNR and short data length.