UHF RFID 射频前端及其编解码设计

射频识别（Radio Frequency Identification，RFID）技术，是一种利用射频通信实现的非接触式的数据采集和自动识别技术（以下通称RFID技术）。而超高频射频识别技术（Ultra High Frequency RFID，UHF RFID）具有识别距离远、识别准确率高、识别速度快、抗干扰能力强等特点而成为当前研发的热点。UHF RFID读写器的难点就在于射频前端电路和基带编解码的设计，它们设计的好坏直接决定了读写器的性能好坏。 本文首先通过介绍UHF RFID读写器射频前端设计的基本原理，采用射频通用收发模块进行射频前端设计的方法，给出了以ADF7020收发芯片为核心的UHF RFID读写器的射频前端的整体设计和具体的实现电路，设计了包括射频收发电路、射频前端匹配电路、滤波电路、环行器电路、功率放大电路等。 其次根据EPC Gen-2的协议标准进行了UHF RFID读写器的基带编码解码的仿真设计，然后开发了以FPGA为核心的完整的数字基带硬件电路，实际调试表明整个基带编解码软件在硬件基带PCB板上运行状况良好，并能对EPC Gen-2的协议标准的命令进行正确的编码解码。 最后通过研究学习软件无线电的理论和开发方法，把UHF　RFID读写器的射频前端分成射频模拟前端和射频数字前端，给出了一种基于软件无线电思想的UHF RFID射频数字前端设计模型，并借助于SIMULINK中的信号处理工具箱对构建的数字前端的进行仿真验证，仿真结果验证了用软件无线电实现UHF RFID数字前端的可行性。

CAN总线及USB技术在路桥收费系统中的应用研究

本文以中国科学院沈阳自动化研究所自动化装备研究室的项目——路桥收费系统为背景。首先阐述了路桥收费系统的组成结构，重点讨论了传统的收费控制子系统的构成和功能。然后在深入分析原有系统不足的基础上，本文提出了采用CAN总线技术和USB接口技术来构建一种全新的收费控制子系统的方法。并对这种方法进行了深入的研究，设计并实现了组成系统所需的核心器件，构成了原型系统，对系统的可行性进行了验证。 CAN总线是目前在中小型测控系统中应用非常广泛的总线之一，它非常适用于收费控制子系统中。USB接口技术是近几年来兴起的新型接口技术，它为外围设备与计算机的连接提供了一种方便、快捷的方法。在我们的系统中以基于USB的新型CAN适配卡代替了以往普通的CAN适配卡，为控制计算机联入CAN网开拓了新思路。 本文详细地阐述了系统中核心器件RS232/CAN、CAN/USB协议转换卡的设计与实现及原型系统的构建和测试方法。主要内容分为系统硬件的设计与实现、系统软件的设计与实现和测试系统的设计与调试三部分。具体包括了核心器件的设计原理、电子元器件的选择、电路原理图的设计、PCB板的制作、硬件的焊接与调试及协议转换卡的固件设计、驱动程序设计、上位机测试程序设计。最后利用所设计的软硬件构建了原型系统并进行了测试。

Correct identification of polychlorinated biphenyls in temperature-programmed GC with ECD detection

A method has been developed for peak identification of PCBs in GC with ECD detection under different temperature programs and isothermal conditions on two commonly used columns (DB-5 and DB-1701). This was achieved by means of accurate calibration of retention times based on the concept of the relative retention index P-i and retention times of the selected PCB internal standards. The P-i was calculated from the predicted retention times with the database of the retention parameters (A, B) and the migration equations. Through comparison of the calibrated and experimental retention times of PCBs in technical samples, it was shown that the developed method was effective for correct PCB comprehensive, quantitative, congener-specific (CQCS) analyses.

Mini-electrochemical detector for microchip electrophoresis

This paper presents the development of a mini-electrochemical detector for microchip electrophoresis. The small size (3.6 x 5.0 cm(2), W x L) of the detector is compatible with the dimension of the microchip. The use of universal serial bus (USB) ports facilitates installation and use of the detector, miniaturizes the detector, and makes it ideal for lab-on-a-chip applications. A fixed 10 M Omega feedback resistance was chosen to convert current of the working electrode to voltage with second gain of 1, 2, 4, 8, 16, 32, 64 and 128 for small signal detection instead of adopting selectable feedback resistance. Special attention has been paid to the power support circuitry and printed circuit board (PCB) design in order to obtain good performance in such a miniature size. The working electrode potential could be varied over a range of +/-2.5 V with a resolution of 0.01 mV. The detection current ranges from -0.3 x 10(-7) A to 2.5 x 10(-7) A and the noise is lower than 1 pA. The analytical performance of the new system was demonstrated by the detection of epinephrine using an integrated PDMS/glass microchip with detection limit of 2.1 mu M (S/N = 3).

Design of miniaturized wireless sensor mote and actuator for building monitoring and control

In this paper, a wireless sensor network mote hardware design and implementation are introduced for building deployment application. The core of the mote design is based on the 8 bit AVR microcontroller, Atmega1281 and 2.4 GHz wireless communication chip, CC2420. The module PCB fabrication is using the stackable technology providing powerful configuration capability. Three main layers of size 25 mm2 are structured to form the mote; these are RF, sensor and power layers. The sensors were selected carefully to meet both the building monitoring and design requirements. Beside the sensing capability, actuation and interfacing to external meters/sensors are provided to perform different management control and data recording tasks. Experiments show that the developed mote works effectively in giving stable data acquisition and owns good communication and power performance.

A simulation-based design method to transfer surface mount RF system to flip-chip die implementation

The flip-chip technology is a high chip density solution to meet the demand for very large scale integration design. For wireless sensor node or some similar RF applications, due to the growing requirements for the wearable and implantable implementations, flip-chip appears to be a leading technology to realize the integration and miniaturization. In this paper, flip-chip is considered as part of the whole system to affect the RF performance. A simulation based design is presented to transfer the surface mount PCB board to the flip-chip die package for the RF applications. Models are built by Q3D Extractor to extract the equivalent circuit based on the parasitic parameters of the interconnections, for both bare die and wire-bonding technologies. All the parameters and the PCB layout and stack-up are then modeled in the essential parts' design of the flip-chip RF circuit. By implementing simulation and optimization, a flip-chip package is re-designed by the parameters given by simulation sweep. Experimental results fit the simulation well for the comparison between pre-optimization and post-optimization of the bare die package's return loss performance. This design method could generally be used to transfer any surface mount PCB to flip-chip package for the RF systems or to predict the RF specifications of a RF system using the flip-chip technology.

Design and implementation of the embedded capacitance layers for decoupling of wireless sensor nodes

In this paper, the embedded capacitance material (ECM) is fabricated between the power and ground layers of the wireless sensor nodes, forming an integrated capacitance to replace the large amount of decoupling capacitors on the board. The ECM material, whose dielectric constant is 16, has the same size of the wireless sensor nodes of 3cm*3cm, with a thickness of only 14μm. Though the capacitance of a single ECM layer being only around 8nF, there are two reasons the ECM layers can still replace the high frequency decoupling capacitors (100nF in our case) on the board. The first reason is: the parasitic inductance of the ECM layer is much lower than the surface mount capacitors'. A smaller capacitance value of the ECM layer could achieve the same resonant frequency of the surface mount decoupling capacitors. Simulation and measurement fit this assumption well. The second reason is: more than one layer of ECM material are utilized during the design step to get a parallel connection of the several ECM capacitance layers, finally leading to a larger value of the capacitance and smaller value of parasitic. Characterization of the ECM is carried out by the LCR meter. To evaluate the behaviors of the ECM layer, time and frequency domain measurements are performed on the power-bus decoupling of the wireless sensor nodes. Comparison with the measurements of bare PCB board and decoupling capacitors solution are provided to show the improvement of the ECM layer. Measurements show that the implementation of the ECM layer can not only save the space of the surface mount decoupling capacitors, but also provide better power-bus decoupling to the nodes.

Impact of non-optimal grounding of the CC2420 RFIC on a 802.15.4 Tyndall sensor wireless mote

The performance of an RF output matching network is dependent on integrity of the ground connection. If this connection is compromised in anyway, additional parasitic elements may occur that can degrade performance and yield unreliable results. Traditionally, designers measure Constant Wave (CW) power to determine that the RF chain is performing optimally, the device is properly matched and by implication grounded. It is shown that there are situations where modulation quality can be compromised due to poor grounding that is not apparent using CW power measurements alone. The consequence of this is reduced throughput, range and reliability. Measurements are presented on a Tyndall Mote using a CC2420 RFIC todemonstrate how poor solder contact between the ground contacts and the ground layer of the PCB can lead tothe degradation of modulated performance. Detailed evaluation that required the development of a new measurement definition for 802.15.4 and analysis is presented to show how waveform quality is affected while the modulated output power remains within acceptable limits.

Assessment of dietary background exposure of the Irish adult population to dioxins and PCBs particularly taking into account additional exposure due to the 2008 Irish dioxin food contamination incident

Irish monitoring data on PCDD/Fs, DL-PCBs and Marker PCBs were collated and combined with Irish Adult Food Consumption Data, to estimate dietary background exposure of Irish adults to dioxins and PCBs. Furthermore, all available information on the 2008 Irish pork dioxin food contamination incident was collated and analysed with a view to evaluate any potential impact the incident may have had on general dioxin and PCB background exposure levels estimated for the adult population in Ireland. The average upperbound daily intake of Irish adults to dioxins Total WHO TEQ (2005) (PCDD/Fs & DLPCBs) from environmental background contamination, was estimated at 0.3 pg/kg bw/d and at the 95th percentile at 1 pg/kg bw/d. The average upperbound daily intake of Irish adults to the sum of 6 Marker PCBs from environmental background contamination ubiquitous in the environment was estimated at 1.6 ng/kg bw/d and at the 95th percentile at 6.8 ng/kg bw/d. Dietary background exposure estimates for both dioxins and PCBs indicate that the Irish adult population has exposures below the European average, a finding which is also supported by the levels detected in breast milk of Irish mothers. Exposure levels are below health based guidance values and/or Body Burdens associated with the TWI (for dioxins) or associated with a NOAEL (for PCBs). Given the current toxicological knowledge, based on biomarker data and estimated dietary exposure, general background exposure of the Irish adult population to dioxins and PCBs is of no human health concern. In 2008, a porcine fat sample taken as part of the national residues monitoring programme led to the detection of a major feed contamination incidence in the Republic of Ireland. The source of the contamination was traced back to the use of contaminated oil in a direct-drying feed operation system. Congener profiles in animal fat and feed samples showed a high level of consistency and pinpointed the likely source of fuel contamination to be a highly chlorinated commercial PCB mixture. To estimate additional exposure to dioxins and PCBs due to the contamination of pig and cattle herds, collection and a systematic review of all data associated with the contamination incident was conducted. A model was devised that took into account the proportion of contaminated product reaching the final consumer during the 90 day contamination incident window. For a 90 day period, the total additional exposure to Total TEQ (PCDD/F &DL-PCB) WHO (2005) amounted to 407 pg/kg bw/90d at the 95th percentile and 1911 pg/kg bw/90d at the 99th percentile. Exposure estimates derived for both dioxins and PCBs showed that the Body Burden of the general population remained largely unaffected by the contamination incident and approximately 10 % of the adult population in Ireland was exposed to elevated levels of dioxins and PCBs. Whilst people in this 10 % cohort experienced quite a significant additional load to the existing body burden, the estimated exposure values do not indicate approximation of body burdens associated with adverse health effects, based on current knowledge. The exposure period was also limited in time to approximately 3 months, following the FSAI recall of contaminated meat immediately on detection of the contamination. A follow up breast milk study on Irish first time mothers conducted in 2009/2010 did not show any increase in concentrations compared to the study conducted in 2002. The latter supports the conclusion that the majority of the Irish adult population was not affected by the contamination incident.

Surface Insulation Resistance Degradation and Electrochemical Migration on Printed Circuit Boards

Widespread adoption of lead-free materials and processing for printed circuit board (PCB) assembly has raised reliability concerns regarding surface insulation resistance (SIR) degradation and electrochemical migration (ECM). As PCB conductor spacings decrease, electronic products become more susceptible to these failures mechanisms, especially in the presence of surface contamination and flux residues which might remain after no-clean processing. Moreover, the probability of failure due to SIR degradation and ECM is affected by the interaction between physical factors (such as temperature, relative humidity, electric field) and chemical factors (such as solder alloy, substrate material, no-clean processing). Current industry standards for assessing SIR reliability are designed to serve as short-term qualification tests, typically lasting 72 to 168 hours, and do not provide a prediction of reliability in long-term applications. The risk of electrochemical migration with lead-free assemblies has not been adequately investigated. Furthermore, the mechanism of electrochemical migration is not completely understood. For example, the role of path formation has not been discussed in previous studies. Another issue is that there are very few studies on development of rapid assessment methodologies for characterizing materials such as solder flux with respect to their potential for promoting ECM. In this dissertation, the following research accomplishments are described: 1). Long-term temp-humidity-bias (THB) testing over 8,000 hours assessing the reliability of printed circuit boards processed with a variety of lead-free solder pastes, solder pad finishes, and substrates. 2). Identification of silver migration from Sn3.5Ag and Sn3.0Ag0.5Cu lead-free solder, which is a completely new finding compared with previous research. 3). Established the role of path formation as a step in the ECM process, and provided clarification of the sequence of individual steps in the mechanism of ECM: path formation, electrodeposition, ion transport, electrodeposition, and filament formation. 4). Developed appropriate accelerated testing conditions for assessing the no-clean processed PCBs' susceptibility to ECM: a). Conductor spacings in test structures should be reduced in order to reflect the trend of higher density electronics and the effect of path formation, independent of electric field, on the time-to-failure. b). THB testing temperatures should be modified according to the material present on the PCB, since testing at 85oC can cause the evaporation of weak organic acids (WOAs) in the flux residues, leading one to underestimate the risk of ECM. 5). Correlated temp-humidity-bias testing with ion chromatography analysis and potentiostat measurement to develop an efficient and effective assessment methodology to characterize the effect of no-clean processing on ECM.

Modelling the performance of lead-Free solder interconnects for copper bumped flip-chip devices

Traditionally, before flip chips can be assembled the dies have to be attached with solder bumps. This process involves the deposition of metal layers on the Al pads on the dies and this is called the under bump metallurgy (UBM). In an alternative process, however, Copper (Cu) columns can be used to replace solder bumps and the UBM process may be omitted altogether. After the bumping process, the bumped dies can be assembled on to the printed circuit board (PCB) by using either solder or conductive adhesives. In this work, the reliability issues of flip chips with Cu column bumped dies have been studied. The flip chip lifetime associated with the solder fatigue failure has been modeled for a range of geometric parameters. The relative importance of these parameters is given and solder volume has been identified as the most important design parameter for long-term reliability. Another important problem that has been studied in this work is the dissolution of protection metals on the pad and Cu column in the reflow process. For small solder joints the amount of Cu which dissolves into the molten solder after the protection layers have worn out may significantly affect solder joint properties.

Modelling the metal arc weldpool

Traditionally, before flip chips can be assembled the dies have to be attached with solder bumps. This process involves the deposition of metal layers on the Al pads on the dies and this is called the under bump metallurgy (UBM). In an alternative process, however, Copper (Cu) columns can be used to replace solder bumps and the UBM process may be omitted altogether. After the bumping process, the bumped dies can be assembled on to the printed circuit board (PCB) by using either solder or conductive adhesives. In this work, the reliability issues of flip chips with Cu column bumped dies have been studied. The flip chip lifetime associated with the solder fatigue failure has been modeled for a range of geometric parameters. The relative importance of these parameters is given and solder volume has been identified as the most important design parameter for long-term reliability. Another important problem that has been studied in this work is the dissolution of protection metals on the pad and Cu column in the reflow process. For small solder joints the amount of Cu which dissolves into the molten solder after the protection layers have worn out may significantly affect solder joint properties.

Finite element modelling of crack detection tests

Four non-destructive tests for determining the length of fatigue cracks within the solder joints of a 2512 surface mount resistor are investigated. The sensitivity of the tests is obtained using finite element analysis with some experimental validation. Three of the tests are mechanically based and one is thermally based. The mechanical tests all operate by applying different loads to the PCB and monitoring the strain response at the top of the resistor. The thermal test operates by applying a heat source underneath the PCB, and monitoring the temperature response at the top of the resistor. From the modelling work done, two of these tests have shown to be sensitive to cracks. Some experimental results are presented but further work is required to fully validate the simulation results.

Response Surface Modeling and Optimisation for Reliable Electronic Products

The aim of integrating computational mechanics (FEA and CFD) and optimization tools is to speed up dramatically the design process in different application areas concerning reliability in electronic packaging. Design engineers in the electronics manufacturing sector may use these tools to predict key design parameters and configurations (i.e. material properties, product dimensions, design at PCB level. etc) that will guarantee the required product performance. In this paper a modeling strategy coupling computational mechanics techniques with numerical optimization is presented and demonstrated with two problems. The integrated modeling framework is obtained by coupling the multi-physics analysis tool PHYSICA - with the numerical optimization package - Visua/DOC into a fuJly automated design tool for applications in electronic packaging. Thermo-mechanical simulations of solder creep deformations are presented to predict flip-chip reliability and life-time under thermal cycling. Also a thermal management design based on multi-physics analysis with coupled thermal-flow-stress modeling is discussed. The Response Surface Modeling Approach in conjunction with Design of Experiments statistical tools is demonstrated and used subsequently by the numerical optimization techniques as a part of this modeling framework. Predictions for reliable electronic assemblies are achieved in an efficient and systematic manner.

Predicting the relationship between reliability and geometric parameters of cu column bumped flip-chips

Cu column bumping is a novel flip chip packaging technique that allows Cu columns to be bonded directly with the dies. It has eliminated the under-bump-metallurgy (UBM) fonnation step of the traditional flip chip manufacturing process. This bumping technique has the potential benefits of simplifying the flip chip manufacturing process, increasing productivity and the UO counts. In this paper, a study of reliability of Cu column bumped flip chips will be presented. Computer modelling methods have been used to predict the shape of solder joints and the response of flip chips to cyclic thermal-mechanical loading. The accumulated plastic strain energy at the corner solder joints has been used as an indicator of the solder joint reliability. Models with a wide range of design parameters have been compared for their reliability. The design parameters that have been investigated are the copper column height and radius, PCB pad radius, solder volume and Cu column wetting height. The relative importance ranking of these parameters has been obtained. The Lead-free solder material 96.5Sn3.5Ag has been used in this modelling work.