Local synthesis and alignment of zinc oxide nanowires in aqueous solution using microheaters

A bottom-up technique for synthesizing transversely suspended zinc oxide nanowires (ZnO NWs) under a zinc nitrate (Zn(NO 3) 2· 6H 2O) and hexamethylenetetramine (HMTA, (CH 2) 6·N 4) solution within a microfabricated device is reported in this paper. The device consists of a microheater which is used to initially create an oxidized ZnO seed layer. ZnO NWs are then locally synthesized by the microheater and electrodes embedded within the devices are used to drive electric field directed horizontal alignment of the nanowires within the device. The entire process is carried out at low temperature. This approach has the potential to considerably simplify the fabrication and assembly of ZnO nanowires on CMOS compatible substrates, allowing for the chemical synthesis to be carried out under near-ambient conditions by locally defining the conditions for nanowire growth on a silicon reactor chip. © 2012 IEEE.

Room-temperature remote-plasma sputtering of c-axis oriented zinc oxide thin films

Highly c-axis oriented ZnO films have been deposited at room temperature with high rates (∼50 nm·min -1) using an innovative remote plasma sputtering configuration, which allows independent control of the plasma density and the sputtering ion energy. The ZnO films deposited possess excellent crystallographic orientation, high resistivity (>10 9 Ω·m), and exhibit very low surface roughness. The ability to increase the sputtering ion energy without causing unwanted Ar + bombardment onto the substrate has been shown to be crucial for the growth of films with excellent c-axis orientation without the need of substrate heating. In addition, the elimination of the Ar + bombardment has facilitated the growth of films with very low defect density and hence very low intrinsic stress (100 MPa for 3 μm-thick films). This is over an order of magnitude lower than films grown with a standard magnetron sputtering system. © 2012 American Institute of Physics.

Near-ultraviolet zinc oxide nanowire sensor using low temperature hydrothermal growth.

Two near-ultraviolet (UV) sensors based on solution-grown zinc oxide (ZnO) nanowires (NWs) which are only sensitive to photo-excitation at or below 400 nm wavelength have been fabricated and characterized. Both devices keep all processing steps, including nanowire growth, under 100 °C for compatibility with a wide variety of substrates. The first device type uses a single optical lithography step process to allow simultaneous in situ horizontal NW growth from solution and creation of symmetric ohmic contacts to the nanowires. The second device type uses a two-mask optical lithography process to create asymmetric ohmic and Schottky contacts. For the symmetric ohmic contacts, at a voltage bias of 1 V across the device, we observed a 29-fold increase in current in comparison to dark current when the NWs were photo-excited by a 400 nm light-emitting diode (LED) at 0.15 mW cm(-2) with a relaxation time constant (τ) ranging from 50 to 555 s. For the asymmetric ohmic and Schottky contacts under 400 nm excitation, τ is measured between 0.5 and 1.4 s over varying time internals, which is ~2 orders of magnitude faster than the devices using symmetric ohmic contacts.

Synthesis of zinc oxide nanostructures by microheaters in the ambient environment

A catalyst-free synthesis of ZnO nanostructures using platinum microheaters under ambient environmental conditions has been developed. Different types of ZnO nanostructures are synthesized from the oxidization of Zn thin film by local heating. The characterization of two shapes of Pt microheaters is investigated and the relationship between the applied power for heat generation and ZnO nanostructure synthesis is investigated by local heating experiments under ambient conditions. Based on the developed heating approach, synthesis area, location, and morphologies of ZnO nanostructures can be controlled through the deposited thickness of Zn layer and applied heating voltages. Furthermore, a connected multiple-structure (Zn-ZnO-Zn) layer is synthesized using combinative multimicroheaters. © 2002-2012 IEEE.

SOI CMOS integrated zinc oxide nanowire for toluene detection

The paper reports on the in-situ growth of zinc oxide nanowires (ZnONWs) on a complementary metal oxide semiconductor (CMOS) substrate, and their performance as a sensing element for ppm (parts per million) levels of toluene vapour in 3000 ppm humid air. Zinc oxide NWs were grown using a low temperature (only 90°C) hydrothermal method. The ZnONWs were first characterised both electrically and through scanning electron microscopy. Then the response of the on-chip ZnONWs to different concentrations of toluene (400-2600ppm) was observed in air at 300°C. Finally, their gas sensitivity was determined and found to lie between 0.1% and 0.3% per ppm. © 2013 IEEE.

Characterization and fabrication of zinc oxide nanowire devices

In this paper, we demonstrate an approach for the local synthesis of ZnO nanowires (ZnO NWs) and the potential for such structures to be incorporated into device applications. Three network ZnO NW devices are fabricated on a chip by using a bottom-up synthesis approach. Microheaters (defined by standard semiconductor processing) are used to synthesize the ZnO NWs under a zinc nitrate (Zn(NO3)2·6H2O) and hexamethylenetetramine (HMTA, (CH2)6·N4) solution. By controlling synthesis parameters, varying densities of networked ZnO NWs are locally synthesized on the chip. The fabricated networked ZnO NW devices are then characterized using UV excitation and cyclic voltammetry (CV) experiments to measure their photoresponse and electrochemical properties. The experimental results show that the techniques and material systems presented here have the potential to address interesting device applications using fabrication methods that are fully compatible with standard semiconductor processing. © 2013 IEEE.

Analysis of amorphous indium-gallium-zinc-oxide thin-film transistor contact metal using Pilling-Bedworth theory and a variable capacitance diode model

It is widely reported that threshold voltage and on-state current of amorphous indium-gallium-zinc-oxide bottom-gate thin-film transistors are strongly influenced by the choice of source/drain contact metal. Electrical characterisation of thin-film transistors indicates that the electrical properties depend on the type and thickness of the metal(s) used. Electron transport mechanisms and possibilities for control of the defect state density are discussed. Pilling-Bedworth theory for metal oxidation explains the interaction between contact metal and amorphous indium-gallium-zinc-oxide, which leads to significant trap formation. Charge trapping within these states leads to variable capacitance diode-like behavior and is shown to explain the thin-film transistor operation. © 2013 AIP Publishing LLC.

Phase perfection in zinc Blende and Wurtzite III-V nanowires using basic growth parameters.

Controlling the crystallographic phase purity of III-V nanowires is notoriously difficult, yet this is essential for future nanowire devices. Reported methods for controlling nanowire phase require dopant addition, or a restricted choice of nanowire diameter, and only rarely yield a pure phase. Here we demonstrate that phase-perfect nanowires, of arbitrary diameter, can be achieved simply by tailoring basic growth parameters: temperature and V/III ratio. Phase purity is achieved without sacrificing important specifications of diameter and dopant levels. Pure zinc blende nanowires, free of twin defects, were achieved using a low growth temperature coupled with a high V/III ratio. Conversely, a high growth temperature coupled with a low V/III ratio produced pure wurtzite nanowires free of stacking faults. We present a comprehensive nucleation model to explain the formation of these markedly different crystal phases under these growth conditions. Critical to achieving phase purity are changes in surface energy of the nanowire side facets, which in turn are controlled by the basic growth parameters of temperature and V/III ratio. This ability to tune crystal structure between twin-free zinc blende and stacking-fault-free wurtzite not only will enhance the performance of nanowire devices but also opens new possibilities for engineering nanowire devices, without restrictions on nanowire diameters or doping.

Deposition of low stress amorphous zinc tin oxide at ambient temperature using a remote plasma sputtering process suitable for delicate substrates

ZnxSnyOz thin films (<100nm thickness), deposited by remote sputtering from a metal target using a confined argon plasma and oxygen gas jet near the sample, were investigated for their material properties. No visible deformation or curl was observed when deposited on plastic. Materials were confirmed to be amorphous and range between 5 and 10 at.% Sn concentration by x-ray diffraction, x-ray photoemission spectroscopy and energydispersive x-ray spectroscopy. Factors affecting the material composition over time are discussed. Depletion of the Sn as the target ages is suspected. © The Electrochemical Society.

DC current rectification using indium-gallium zinc oxide-based selfswitching diodes

Self-switching diodes have been fabricated within a single layer of indium-gallium zinc oxide (IGZO). Current-voltage (I-V) measurements show the nanometer-scale asymmetric device gave a diode-like response. Full current rectification was achieved using very narrow channel widths of 50nm, with a turn-on voltage, Von, of 2.2V. The device did not breakdown within the -10V bias range measured. This single diode produced a current of 0.1μA at 10V and a reverse current of less than 0.1nA at -10V. Also by adjusting the channel width for these devices, Von could be altered; however, the effectiveness of the rectification also changed. © 2013 IEEE.

A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination

It has been previously observed that thin film transistors (TFTs) utilizing an amorphous indium gallium zinc oxide (a-IGZO) semiconducting channel suffer from a threshold voltage shift when subjected to a negative gate bias and light illumination simultaneously. In this work, a thermalization energy analysis has been applied to previously published data on negative bias under illumination stress (NBIS) in a-IGZO TFTs. A barrier to defect conversion of 0.65-0.75 eV is extracted, which is consistent with reported energies of oxygen vacancy migration. The attempt-to-escape frequency is extracted to be 10 6-107 s-1, which suggests a weak localization of carriers in band tail states over a 20-40 nm distance. Models for the NBIS mechanism based on charge trapping are reviewed and a defect pool model is proposed in which two distinct distributions of defect states exist in the a-IGZO band gap: these are associated with states that are formed as neutrally charged and 2+ charged oxygen vacancies at the time of film formation. In this model, threshold voltage shift is not due to a defect creation process, but to a change in the energy distribution of states in the band gap upon defect migration as this allows a state formed as a neutrally charged vacancy to be converted into one formed as a 2+ charged vacancy and vice versa. Carrier localization close to the defect migration site is necessary for the conversion process to take place, and such defect migration sites are associated with conduction and valence band tail states. Under negative gate bias stressing, the conduction band tail is depleted of carriers, but the bias is insufficient to accumulate holes in the valence band tail states, and so no threshold voltage shift results. It is only under illumination that the quasi Fermi level for holes is sufficiently lowered to allow occupation of valence band tail states. The resulting charge localization then allows a negative threshold voltage shift, but only under conditions of simultaneous negative gate bias and illumination, as observed experimentally as the NBIS effect. © 2014 AIP Publishing LLC.

Molecular cloning and characterization of the copper/zinc and manganese superoxide dismutase genes from the human parasite Clonorchis sinensis

A copper/zinc superoxide dismutase (Cu/ZnSOD) gene and a manganese superoxide dismutase (MnSOD) gene of the human parasite Clonorchis sinensis have been cloned and their gene products functionally characterized. Genes Cu/ZnSOD and MnSOD encode proteins of 16 kDa and 25.4 kDa, respectively. The deduced amino acid sequences of the two genes contained highly conserved residues required for activity and secondary structure formation of Cu/ZnSOD and MnSOD, respectively, and show up to 73.7% and 75.4% identities with their counterparts in other animals. The genomic DNA sequence analysis of Cu/ZnSOD gene revealed this as an intronless gene. Inhibitor studies with purified recombinant Cu/ ZnSOD and MnSOD, both of which were functionally expressed in Escherichia coli, confirmed that they are copper/zinc and manganese-containing SOD, respectively. Immunoblots showed that both C. sinensis Cu/ZnSOD and MnSOD should be antigenic for humans, and both, especially the C. sinensis MnSOD, exhibit extensive cross-reactions with sera of patients infected by other trematodes or cestodes. RT-PCR and SOD activity staining of parasite lysates indicate that there are no significant differences in mRNA level or SOD activity for both species of SOD, indicating cytosolic Cu/ZnSOD and MnSOD might play a comparatively important role in the C. sinensis antioxidant system.

Fourier spectrum based extraction of an equivalent trap state density in indium gallium zinc oxide transistors

Segregating the dynamics of gate bias induced threshold voltage shift, and in particular, charge trapping in thin film transistors (TFTs) based on time constants provides insight into the different mechanisms underlying TFTs instability. In this Letter we develop a representation of the time constants and model the magnitude of charge trapped in the form of an equivalent density of created trap states. This representation is extracted from the Fourier spectrum of the dynamics of charge trapping. Using amorphous In-Ga-Zn-O TFTs as an example, the charge trapping was modeled within an energy range of ΔEt 0.3 eV and with a density of state distribution as Dt(Et-j)=Dt0exp(-ΔEt/ kT)with Dt0 = 5.02 × 1011 cm-2 eV-1. Such a model is useful for developing simulation tools for circuit design. © 2014 AIP Publishing LLC.