RFID in the warehouse:a literature analysis (1995-2010) of its applications, benefits, challenges and future trends

Radio Frequency Identification (RFID) has been identified as a crucial technology for the modern 21st century knowledge-based economy. Some businesses have realised benefits of RFID adoption through improvements in operational efficiency, additional cost savings, and opportunities for higher revenues. RFID research in warehousing operations has been less prominent than in other application domains. To investigate how RFID technology has had an impact in warehousing, a comprehensive analysis of research findings available from articles through leading scientific article databases has been conducted. Articles from years 1995 to 2010 have been reviewed and analysed with respect to warehouse operations, RFID application domains, benefits achieved and obstacles encountered. Four discussion topics are presented covering RFID in warehousing focusing on its applications, perceived benefits, obstacles to its adoption and future trends. This is aimed at elucidating the current state of RFID in the warehouse and providing insights for researchers to establish new research agendas and for practitioners to consider and assess the adoption of RFID in warehousing functions. © 2013 Elsevier B.V.

An order batching and processing heuristic to address aisle congestion in a manual order picking warehouse with order due dates

A heuristic for batching orders in a manual order-picking warehouse has been developed. It prioritizes orders based on due time to prevent mixing of orders of different priority levels. The order density of aisles criterion is used to form batches. It also determines the number of pickers required and assigns batches to pickers such that there is a uniform workload per unit of time. The effectiveness of the heuristic was studied by observing computational time and aisle congestion for various numbers of total orders and number of orders that form a batch. An initial heuristic performed well for small number of orders, but for larger number of orders, a partitioning technique is computationally more efficient, needing only minutes to solve for thousands of orders, while preserving 90% of the batch quality obtained with the original heuristic. Comparative studies between the heuristic and other published heuristics are needed. ^

Improving storage performance through layout optimizations

Disk drives are the bottleneck in the processing of large amounts of data used in almost all common applications. File systems attempt to reduce this by storing data sequentially on the disk drives, thereby reducing the access latencies. Although this strategy is useful when data is retrieved sequentially, the access patterns in real world workloads is not necessarily sequential and this mismatch results in storage I/O performance degradation. This thesis demonstrates that one way to improve the storage performance is to reorganize data on disk drives in the same way in which it is mostly accessed. We identify two classes of accesses: static, where access patterns do not change over the lifetime of the data and dynamic, where access patterns frequently change over short durations of time, and propose, implement and evaluate layout strategies for each of these. Our strategies are implemented in a way that they can be seamlessly integrated or removed from the system as desired. We evaluate our layout strategies for static policies using tree-structured XML data where accesses to the storage device are mostly of two kinds—parent-to-child or child-to-sibling. Our results show that for a specific class of deep-focused queries, the existing file system layout policy performs better by 5–54X. For the non-deep-focused queries, our native layout mechanism shows an improvement of 3–127X. To improve performance of the dynamic access patterns, we implement a self-optimizing storage system that performs rearranges popular block accesses on a dedicated partition based on the observed workload characteristics. Our evaluation shows an improvement of over 80% in the disk busy times over a range of workloads. These results show that applying the knowledge of data access patterns for allocation decisions can substantially improve the I/O performance.

Improving Storage Performance Through Layout Optimizations

Disk drives are the bottleneck in the processing of large amounts of data used in almost all common applications. File systems attempt to reduce this by storing data sequentially on the disk drives, thereby reducing the access latencies. Although this strategy is useful when data is retrieved sequentially, the access patterns in real world workloads is not necessarily sequential and this mismatch results in storage I/O performance degradation. This thesis demonstrates that one way to improve the storage performance is to reorganize data on disk drives in the same way in which it is mostly accessed. We identify two classes of accesses: static, where access patterns do not change over the lifetime of the data and dynamic, where access patterns frequently change over short durations of time, and propose, implement and evaluate layout strategies for each of these. Our strategies are implemented in a way that they can be seamlessly integrated or removed from the system as desired. We evaluate our layout strategies for static policies using tree-structured XML data where accesses to the storage device are mostly of two kinds - parent-tochild or child-to-sibling. Our results show that for a specific class of deep-focused queries, the existing file system layout policy performs better by 5-54X. For the non-deep-focused queries, our native layout mechanism shows an improvement of 3-127X. To improve performance of the dynamic access patterns, we implement a self-optimizing storage system that performs rearranges popular block accesses on a dedicated partition based on the observed workload characteristics. Our evaluation shows an improvement of over 80% in the disk busy times over a range of workloads. These results show that applying the knowledge of data access patterns for allocation decisions can substantially improve the I/O performance.

Portrait of Carol Spinka, commercial artist preparing layout

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Ambulance Treatment Space Ergonomic Layout

This is the first time a multidisciplinary team has employed an iterative co-design method to determine the ergonomic layout of an emergency ambulance treatment space. This process allowed the research team to understand how treatment protocols were performed and developed analytical tools to reach an optimum configuration towards ambulance design standardisation. Fusari conducted participatory observations during 12-hour shifts with front-line ambulance clinicians, hospital staff and patients to understand the details of their working environments whilst on response to urgent and emergency calls. A simple yet accurate 1:1 mock-up of the existing ambulance was built for detailed analysis of these procedures through simulations. Paramedics were called in to participate in interviews and role-playing inside the model to recreate tasks, how they are performed, the equipment used and to understand the limitations of the current ambulance. The use of Link Analysis distilled 5 modes of use. In parallel, an exhaustive audit of all equipment and consumables used in ambulances was performed (logging and photography) to define space use. These developed 12 layout options for refinement and CAD modelling and presented back to paramedics. The preferred options and features were then developed into a full size test rig and appearance model. Two key studies informed the process. The 2005 National Patient Safety Agency funded study “Future Ambulances” outlined 9 design challenges for future standardisation of emergency vehicles and equipment. Secondly, the 2007 EPSRC funded “Smart Pods” project investigated a new system of mobile urgent and emergency medicine to treat patients in the community. A full-size mobile demonstrator unit featuring the evidence-based ergonomic layout was built for clinical tests through simulated emergency scenarios. Results from clinical trials clearly show that the new layout improves infection control, speeds up treatment, and makes it easier for ambulance crews to follow correct clinical protocols.

Melhoria de fluxos no armazém de componentes da Bosch Termotecnologia S.A.

A gestão de um armazém de componentes de uma qualquer empresa produtiva é uma das principais tarefas a desempenhar no seio desta, pois a mesma afecta toda a cadeia de abastecimento de entrega do produto final, sendo o armazém de componentes o início da cadeia interna. Qualquer dificuldade que surja no desenrolar das actividades associadas poderá causar impactos prejudiciais nos processos consequentes. A melhoria do principal processo do armazém, correspondente à satisfação dos pedidos de material dos processos a jusante, é algo que trará benefícios a toda a cadeia, ao mesmo tempo que são melhoradas as condições de trabalho, eliminando o desperdício e tornando o processo mais eficiente. Não obstante deste processo, ainda existe a necessidade de recolher e gerir informações referentes aos diferentes processos do armazém da maneira mais rápida possível, para actuar de acordo com as necessidades. A falta de informação relativamente ao estado de um processo também poderá influenciar os processos seguintes de forma negativa. O projecto aqui apresentado foi realizado no armazém de componentes da Bosch Termotecnologia S.A., em Aveiro, tendo como objectivo mostrar a importância da movimentação de material e também de informação dentro desta área, criando ao mesmo tempo a melhoria tanto dos fluxos de material como dos fluxos de informação. Serão apresentadas diferentes implementações que foram desenvolvidas com o intuito de criar melhoria nos fluxos: a criação de novos fluxos de informação para o processo de recepção de material, com o intuito de recolher informação que até agora não era perceptível, para depois actuar na melhoria do processo; a criação de áreas dedicadas dentro da área de picking, de modo a atingir uma redução no número de colaboradores afectos ao processo de picking; a implementação de uma célula de repacking, de modo a remover esta actividade do processo de picking; bem como todas as actividades realizadas com o objectivo de implementar as melhorias propostas.

ONTOLOGIAS DE DOMÍNIO PARA CONVERSÃO DE CONHECIMENTO TÁCITO EM EXPLÍCITO NA MODELAGEM DE REQUISITOS DE SOFTWARE: APLICAÇÃO EM UM PROJETO DE DATA WAREHOUSE PARA A INDÚSTRIA MÉDICA FARMACÊUTICA

A pesquisa tem o objetivo de contribuir para os estudos relacionados ao desenvolvimento de software, mais especificamente à fase de levantamento de requisitos da Engenharia de Software, ao esclarecer como um método não muito popular, a construção de Ontologias de Domínio, pode ajudar na definição de requisitos de qualidade, que consequentemente contribuem para o sucesso de projetos de implementação de sistemas de informação.

Melhoria do processo de armazenagem do armazém de matérias-primas e de embalagem da Nestlé Portugal

O presente relatório de projeto de tese aborda o estudo da temática da gestão de armazéns, bem como o estudo de ferramentas de melhoria contínua. Nele, é apresentado um caso de estudo realizado na Nestlé Portugal – Fábrica de Avanca. Numa fase introdutória e preparatória ao projeto, foi realizado um trabalho de pesquisa e compreensão de conhecimentos base para definir quais os objetivos a alcançar e pontos de melhoria. Esta base serviu de pilar de conhecimento para o desenvolvimento do caso de estudo. O caso de estudo consistiu em analisar o sistema de armazenagem, tendo-se para isso simulado o desempenho atual do armazém de modo a otimizar os espaços de armazenagem. Para além disso, avaliou-se o layout do armazém em função da rotatividade dos materiais com recurso à análise ABC e ao estudo de tempos. As oportunidades de melhoria ao nível dos processos de armazenagem refletem-se no sistema de armazenagem em que o ideal seria uma reestruturação ao nível do sistema de armazenagem (estantes com racks convencionais) e ao nível do layout do armazém (segundo a classificação ABC).

Security through Obscurity: Layout Obfuscation of Digital Integrated Circuits using Don't Care Conditions

Contemporary integrated circuits are designed and manufactured in a globalized environment leading to concerns of piracy, overproduction and counterfeiting. One class of techniques to combat these threats is circuit obfuscation which seeks to modify the gate-level (or structural) description of a circuit without affecting its functionality in order to increase the complexity and cost of reverse engineering. Most of the existing circuit obfuscation methods are based on the insertion of additional logic (called “key gates”) or camouflaging existing gates in order to make it difficult for a malicious user to get the complete layout information without extensive computations to determine key-gate values. However, when the netlist or the circuit layout, although camouflaged, is available to the attacker, he/she can use advanced logic analysis and circuit simulation tools and Boolean SAT solvers to reveal the unknown gate-level information without exhaustively trying all the input vectors, thus bringing down the complexity of reverse engineering. To counter this problem, some ‘provably secure’ logic encryption algorithms that emphasize methodical selection of camouflaged gates have been proposed previously in literature [1,2,3]. The contribution of this paper is the creation and simulation of a new layout obfuscation method that uses don't care conditions. We also present proof-of-concept of a new functional or logic obfuscation technique that not only conceals, but modifies the circuit functionality in addition to the gate-level description, and can be implemented automatically during the design process. Our layout obfuscation technique utilizes don’t care conditions (namely, Observability and Satisfiability Don’t Cares) inherent in the circuit to camouflage selected gates and modify sub-circuit functionality while meeting the overall circuit specification. Here, camouflaging or obfuscating a gate means replacing the candidate gate by a 4X1 Multiplexer which can be configured to perform all possible 2-input/ 1-output functions as proposed by Bao et al. [4]. It is important to emphasize that our approach not only obfuscates but alters sub-circuit level functionality in an attempt to make IP piracy difficult. The choice of gates to obfuscate determines the effort required to reverse engineer or brute force the design. As such, we propose a method of camouflaged gate selection based on the intersection of output logic cones. By choosing these candidate gates methodically, the complexity of reverse engineering can be made exponential, thus making it computationally very expensive to determine the true circuit functionality. We propose several heuristic algorithms to maximize the RE complexity based on don’t care based obfuscation and methodical gate selection. Thus, the goal of protecting the design IP from malicious end-users is achieved. It also makes it significantly harder for rogue elements in the supply chain to use, copy or replicate the same design with a different logic. We analyze the reverse engineering complexity by applying our obfuscation algorithm on ISCAS-85 benchmarks. Our experimental results indicate that significant reverse engineering complexity can be achieved at minimal design overhead (average area overhead for the proposed layout obfuscation methods is 5.51% and average delay overhead is about 7.732%). We discuss the strengths and limitations of our approach and suggest directions that may lead to improved logic encryption algorithms in the future. References: [1] R. Chakraborty and S. Bhunia, “HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493–1502, 2009. [2] J. A. Roy, F. Koushanfar, and I. L. Markov, “EPIC: Ending Piracy of Integrated Circuits,” in 2008 Design, Automation and Test in Europe, 2008, pp. 1069–1074. [3] J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, “Security Analysis of Integrated Circuit Camouflaging,” ACM Conference on Computer Communications and Security, 2013. [4] Bao Liu, Wang, B., "Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks,"Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , vol., no., pp.1,6, 24-28 March 2014.