A novel heavily doped drift-auxiliary cathode lateral insulated gate transistor structure

A novel CMOS-compatible, heavily doped drift auxiliary cathode lateral insulated gate transistor (HDD-ACLIGT) structure is analyzed using two-dimensional device simulation techniques. Simulation results indicate that low on-resistance and a fast turn-off time of less than 50 ns can be achieved by incorporating an additional n+ region which is self-aligned to the gate between the p+ auxiliary cathode and the p well, together with an extended p buried layer in an anode-shorted modified lateral insulated gate transistor (MLIGT) structure. The on-state and its transient performance are analyzed in detail. The on-state performances of the HDD-ACLIGT and the MLIGT are compared and discussed. The results indicate that the HDD-ACLIGT structure is well suited for HVICs. The device is also well suited for integration with self-aligned digital CMOS.

Stepped gate polysilicon thin film transistor for large area power applications

For the first time, we report a new poly-Si stepped gate Thin Film Transistor (SG TFT) on glass. The Density of States extracted from measured I-V characteristics has been used to evaluate the device performance with a two dimensional device simulator. The results show that the three-terminal SG TFT device has a switching speed comparable to a low voltage structure and the high on-current capability of a metal field plate (MFP) TFT and the potential for comparable breakdown characteristics.

Carbon based bottom gate thin film transistor

This paper describes the fabrication and characterization of a carbon based, bottom gate, thin film transistor (TFT). The active layer is formed from highly sp2 bonded nitrogenated amorphous carbon (a-C:N) which is deposited at room temperature using a filtered cathodic vacuum arc technique. The TFT shows p-channel operation. The device exhibits a threshold voltage of 15 V and a field effect mobility of 10-4 cm2 V-1 s-1 . The valence band tail of a-C:N is observed to be much shallower than that of a-Si:H, but does not appear to severely impede the shift of the Fermi level. This may indicate that a significant proportion of the a-C tail states can still contribute to conduction.

Modeling of MOS-side carrier injection in trench-gate IGBTs

A compact trench-gate IGBT model that captures MOS-side carrier injection is developed. The model retains the simplicity of a one-dimensional solution to the ambipolar diffusion equation, but at the same time captures MOS-side carrier injection and its effects on steady-state carrier distribution in the drift region and on switching waveforms. © 2007 IEEE.

Effect of gate dielectric scaling in nanometer scale vertical thin film transistors

A short channel vertical thin film transistor (VTFT) with 30 nm SiN x gate dielectric is reported for low voltage, high-resolution active matrix applications. The device demonstrates an ON/OFF current ratio as high as 10 9, leakage current in the fA range, and a sub-threshold slope steeper than 0.23 V/dec exhibiting a marked improvement with scaling of the gate dielectric thickness. © 2011 American Institute of Physics.

Steady-state analytical model for the trench insulated gate bipolar transistor

A steady-state, physically-based analytical model for the Trench Insulated Gate Bipolar Transistor which accounts for a combined PIN diode - PNP transistor carrier dynamics is proposed. Previous models (i.e. PIN model and PNP transistor model) cannot account properly for the carrier dynamics in Trench IGBT since neither the PNP transistor nor the PIN diode effect can be neglected. An optimized Trench IGBT with a large ratio between the accumulation layer and the cell size leads to substantially improved on-state characteristics, which makes the Trench IGBT potentially the most attractive device in the area of high voltage fast switching devices.

Parameters influencing the performance of an IGBT gate drive

This paper presents an improvement of an IGBT gate drive implementing Active Voltage Control (AVC), and investigates the impact of various parameters affecting its performance. The effects of the bandwidths of various elements and the gains of AVC are shown in simulation and experimentally. Also, the paper proposes connecting a small Active Snubber between the IGBT collector and its gate integrated within the AVC. The effect of this snubber on enhancing the stability of the gate drive is demonstrated. It will be shown that using a wide bandwidth operational amplifier and integrating the Active Snubber within the gate drive reduces the minimum gate resistor required to achieve stability of the controller. Consequently, the response time of the IGBT to control signals is significantly reduced, the switching losses then can be minimised and, hence, the performance of gate drive as whole is improved. This reflects positively on turn-off and turn-on transitions achieving voltage sharing between the IGBTs connected in series to construct a higher voltage switch, making series IGBTs a feasible practice. ©2008 IEEE.

A 660MHz ZVS DC-DC converter using gate-driver charge-recycling in 0.18μm CMOS with an integrated output filter

The design and manufacture of a prototype chip level power supply is described, with both simulated and experimental results. Of particular interest is the inclusion of a fully integrated on-chip LC filter. A high switching frequency of 660MHz and the design of a device drive circuit reduce losses by supply stacking, low-swing signaling and charge recycling. The paper demonstrates that a chip level converter operating at high frequency can be built and shows how this can be achieved, using zero voltage switching techniques similar to those commonly used in larger converters. Both simulations and experimental data from a fabricated circuit in 0.18μm CMOS are included. The circuit converts 2.2V to 0.75∼1.0V at ∼55mA. ©2008 IEEE.