Mixed-signal analog-digital circuits design on the pre-diffused digital array using trapezoidal association of transistors

The mixed-signal and analog design on a pre-diffused array is a challenging task, given that the digital array is a linear matrix arrangement of minimum-length transistors. To surmount this drawback a specific discipline for designing analog circuits over such array is required. An important novel technique proposed is the use of TAT (Trapezoidal Associations of Transistors) composite transistors on the semi-custom Sea-Of-Transistors (SOT) array. The analysis and advantages of TAT arrangement are extensively analyzed and demonstrated, with simulation and measurement comparisons to equivalent single transistors. Basic analog cells were also designed as well in full-custom and TAT versions in 1.0mm and 0.5mm digital CMOS technologies. Most of the circuits were prototyped in full-custom and TAT-based on pre-diffused SOT arrays. An innovative demonstration of the TAT technique is shown with the design and implementation of a mixed-signal analog system, i. e., a fully differential 2nd order Sigma-Delta Analog-to-Digital (A/D) modulator, fabricated in both full-custom and SOT array methodologies in 0.5mm CMOS technology from MOSIS foundry. Three test-chips were designed and fabricated in 0.5mm. Two of them are IC chips containing the full-custom and SOT array versions of a 2nd-Order Sigma-Delta A/D modulator. The third IC contains a transistors-structure (TAT and single) and analog cells placed side-by-side, block components (Comparator and Folded-cascode OTA) of the Sigma-Delta modulator.

Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

Metamaterial inspired improved antennas and circuits

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior

Up-converter nanophosphor Y2O2S:Er,Yb aminofunctionalized containing or not spherical silica conjugated with BSA

This work reports on the study of the nanophosphor. Y2O2S:Er(2%),Yb(1%) obtained from polymeric resin to be evaluated as fluorescent label with Suitable features to conjugate with bio-molecules for bioassay up-converting phosphor technology (UPT) application A conjugation protocol between bovine serum albumin (BSA) and the aminofunctionalized nanophosphor containing or not spherical silica was established UV-vis results indicated an effective conjugation between nanophosphor particles and the protein up-conversion measurements under 980 nm excitation performed for samples before and after aminofunctionalization showed that nanophosphor particles luminescence features keep unchanged in all cases All results suggest that the adapted protocol is feasible to provide a nanoparticle-protein effective conjugation preserving nanophosphor optical features The presence of spherical silica can be considered advantageous to increase conjugation efficiency Therefore. the developed procedure is applicable for future conjugations between the chosen nanophosphor and the streptavidin protein chat takes part in the well known self-recognition system avidin-biotin. (C) 2009 Elsevier B.V All rights reserved.

A novel voltage step-down/up ZCS-PWM Zeta converter

This paper presents an analysis of a novel pulse-width-modulated (PWM) voltage step-down/up Zeta converter, featuring zero-current-switching (ZCS) at the active switches. The applications in de to de and ac to de (rectifier) operation modes are used as examples to illustrate the performance of this new ZCS-PWM Zeta converter. Regarding to the new ZCS-PWM Zeta rectifier proposed, it should be noticed that the average-current mode control is used in order to obtain a structure with high power-factor (HPF) and low total harmonic distortion (THD) at the input current.Two active switches (main and auxiliary transistors), two diodes, two small resonant inductors and one small resonant capacitor compose the novel ZCS-PWM soft-commutation cell, used in these new ZCS-PWM Zeta converters. In this cell, the turn-on of the active switches occurs in zero-current (ZC) and their turn-off in zero-current and zero-voltage (ZCZV). For the diodes, their turn-on process occurs in zero-voltage (ZV) and their reverse-recovery effects over the active switches are negligible. These characteristics make this cell suitable for Insulated-Gate Bipolar Transistors (IGBTs) applications.The main advantages of these new Zeta converters, generated from the new soft-commutation cell proposed, are possibility of obtaining isolation (through their accumulation inductors), and high efficiency, at wide load range. In addition, for the rectifier application, a high power factor and low THD in the input current ran be obtained, in agreement with LEC 1000-3-2 standards.The principle of operation, the theoretical analysis and a design example for the new de to de Zeta converter operating in voltage step-down mode are presented. Experimental results are obtained from a test unit with 500W output power, 110V(dc) output voltage, 220V(dc) input voltage, operating at 50kHz switching frequency. The efficiency measured at rated toad is equal to 97.3%for this new Zeta converter.Finally, the new Zeta rectifier is analyzed, and experimental results from a test unit rated at 500W output power, 110V(dc) output voltage, 220V(rms) input voltage, and operating at 50kHz switching frequency, are presented. The measured efficiency is equal to 96.95%, the power-factor is equal to 0.98, and the input current THD is equal to 19.07%, for this new rectifier operating at rated load.

Allocation of protective devices in distribution circuits using nonlinear programming models and genetic algorithms

The optimized allocation of protective devices in strategic points of the circuit improves the quality of the energy supply and the system reliability index. This paper presents a nonlinear integer programming (NLIP) model with binary variables, to deal with the problem of protective device allocation in the main feeder and all branches of an overhead distribution circuit, to improve the reliability index and to provide customers with service of high quality and reliability. The constraints considered in the problem take into account technical and economical limitations, such as coordination problems of serial protective devices, available equipment, the importance of the feeder and the circuit topology. The use of genetic algorithms (GAs) is proposed to solve this problem, using a binary representation that does (1) or does not (0) show allocation of protective devices (reclosers, sectionalizers and fuses) in predefined points of the circuit. Results are presented for a real circuit (134 busses), with the possibility of protective device allocation in 29 points. Also the ability of the algorithm in finding good solutions while improving significantly the indicators of reliability is shown. (C) 2003 Elsevier B.V. All rights reserved.

Variable-Structure Control Design of Switched Systems With an Application to a DC-DC Power Converter

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

DCM Boost interleaved converter for operation in AC and DC to trolleybus application

This paper is based on the development and experimental analysis of a DCM Boost interleaved converter suitable for application in traction systems of electrical vehicles pulled by electrical motors (Trolleybus), which are powered by urban DC or AC distribution networks. This front-end structure is capable of providing significant improvements in trolleybuses systems and in the urban distribution network costs, and efficiency. The architecture of proposed converter is composed by five boost power cells in interleaving connection, operating in discontinuous conduction mode. Furthermore, the converter can operate as AC-DC converter, or as DC-DC converter providing the proper DC output voltage range required by DC or AC adjustable speed drivers. Therefore, when supplied by single-phase AC distribution networks, and operating as AC-DC converter, it is capable to provide high power factor, reduced harmonic distortion in the input current, complying with the restrictions imposed by the IEC 61000-3-4 standards. The digital controller has been implemented using a low cost FPGA and developed totally using a hardware description language VHDL and fixed point arithmetic. Thus, two control strategies are evaluated considering the compliance with input current restrictions imposed by IEC 61000-3-4 standards, the regular PWM modulation and a current correction PWM modulation. In order to verify the feasibility and performance of the proposed system, experimental results from a 15 kW low power scale prototype are presented, operating in DC and AC conditions.

Power Factor Correction Boost Converter Based on the Three-State Switching Cell

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Vibration energy harvesting using piezoelectric transducer and non-controlled rectifiers circuits

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Settling analysis of MOS regulated current mirrors applied to micropower D/A converters

This paper provides an insight to the trade-off between settling time and power consumption in regulated current mirrors as building parts in micropower current-switching D/A converters. The regulation-loop frequency characteristic is obtained and difficulties to impose a dominant-pole condition to the resulting 2nd-order system are evaluated. Raising pole frequencies in micropower circuits, while meeting consumption requirements, is basically limited by parasitic capacitances. For such cases, an alternative is to impose a twin-pole condition in which design constraints are somewhat relieved and settling slightly improved. Relationships between pole frequencies, transistor geometry and bias are established and design guidelines for regulated current mirrors founded. By placing loop-transistors in either weak or strong inversion, small (W/L) ratios are allowed and stray capacitances reduced. Simulated waveforms suggest a good agreement with theory. The proposed approach applied to the design of a micropower current-mode D/A converter improves both simulated and experimental settling performance.

Morphological and luminescent studies on nanosized Er, Yb-Yttrium oxide up-converter prepared from different precursors

In this paper, we report luminescent and morphological studies with yttrium oxide samples doped with ytterbium and erbium. The samples were prepared by the combustion method and also from different precursors: oxalate, basic carbonate and polymeric resin. All powders were identified Lis being an yttrium oxide with a C-form structure, independent of the employed precursor. From mean crystallite size measurements, it was verified that oxides prepared through the polymeric precursor and combustion methods lead to the smallest crystallite size. Particle shape and size were investigated by SEM and TEM, and showed that both the oxalate precursor and the combustion methods do not provide oxide materials of suitable shape or size, on the other hand. The basic carbonate and polymeric precursors resulted in spherically shaped particles with an average diameter of 90 and 15 run. respectively, Upon 980 run diode laser excitation, green and red emission lines were detected for all samples and were assigned to the H-2(11/2) S-4(3/2) -> I-4(15/2) and (4)Fg(9/2) -> 4I(15/12) transitions, respectively. Such transitions are characteristic for Er3+ and result from energy transfer from Yb3+ energy levels, F-2(7/2) -> F-2(5/2). A relationship between the decrease in the mean crystallite size and the enhancement in red emission was also established as well as the influence of the presence of a high percentage of Yb-3 Both factors promote ET from Yb3+ (F-2(5/2)) to Er3+ (I-4(11/2)). (c) 2004 Elsevier B.V. All rights reserved.

A procedure to estimate parameters of a line segment taking into account its representation through pi circuits: Theoretical development

The objective of this paper is to show an alternative methodology to estimate per unit length parameters of a line segment of a transmission line. With this methodology the line segment parameters can be obtained starting from the phase currents and -voltages in receiving and sending end of the line segment. If the line segment is represented as being one or more pi circuits whose frequency dependent parameters are considered lumped, its impedance and admittance can be easily expressed as functions of the currents and voltages at the sending and receiving end. Because we are supposing that voltages and currents at the sending and receiving end of the tine segment (in frequency domain) are known, it is possible to obtains its impedance and admittance and consequently its per unit length longitudinal and transversal parameters. The procedure will be applied to estimate the longitudinal and transversal parameters of a small segment of a single-phase line that is already built.

Three- phase four-wire circuits interpretation by means of different power theories

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Application of pi Circuits for Simulation of Corona Effect in Transmission Lines

In this article, it is represented by state variables phase a transmission line which parameters are considered frequency independently and frequency dependent. Based on previous analyses, it is used the reasonable number of p circuits and the number of blocks composed by parallel resistor and inductor for reduction of numerical oscillations. It is analyzed the influence of the increase of the RL parallel blocks in the obtained results. The RL parallel blocks are used for inclusion of the frequency influence in the transmission line longitudinal parameter. It is a simple model that is been used by undergraduate students for simulation of traveling wave phenomena in transmission lines. Considering the model without frequency influence, it is included a representation of the corona effect. Some simulations are carried considering the corona effect and they are compared to the results without this phenomenon.