DTC Technique for Induction Machine based Integrated Starter-Generator of an Automobile

This paper mainly concentrates on the application of the direct torque control (DTC) technique for the induction machine based integrated startergenerator (ISG) for automobile applications. It also discusses in brief about the higher DC bus voltage requirements in the automobiles i.e. present 14V system vs. 42V system to meet the power requirements, modes of operation of ISG, electric machine and the drive selection for the ISG,description of DTC technique, simulation and experimental results, and implementation.

A Computationally Efficient PWM Algorithm for Multilevel Inverters

Centred space vector PWM (CSVPWM) technique is popularly used for three level voltage source inverters. The reference voltage vector is synthesized by time-averaging of the three nearest voltage vectors produced by the inverter. Identifying the three voltage vectors, and calculation of the dwelling time for each vector are both computationally intensive. This paper analyses the process of PWM generation in CSVPWM. This analysis breaks up a three-level inverter into six different conceptual two level inverters in different regions of the fundamental cycle. Control of 3-level inverter is viewed as the control of the appropriate 2-level inverter. The analysis leads to a systematic simplification of the computations involved, finally resulting in a computationally efficient PWM algorithm. This algorithm exploits the equivalence between triangle comparison and space vector approaches to PWM generation. This algorithm does not involve any 3-phase/2-phase or 2-phase/3-phase transformation. This also does not involve any transformation from rectangular to polar coordinates, and vice versa. Further no evaluation of trigonometric functions is necessary. This algorithm also provides for the mitigation of DC neutral point unbalance, and is well suited to digital implementation. Simulation and experimental results are presented.

Organometallic chemistry of diphosphazane ligands

The reactions of a range of acyclic, cyclic and bicyclic diphosphazanes with several transition metal organometallic derivatives have been investigated. The structures of the products have been deduced from IR and NMR spectroscopic data and confirmed by single crystal X-ray analysis of a few representative compounds.

Three Dimensional Line-Clipping by Systematic Enumeration

Three dimensional clipping is a critical component of the 3D graphics pipeline. A new 3D clipping algorithm is presented in this paper. An efficient 2D clipping routine reported earlier has been used as a submodule. This algorithm uses a new classification scheme for lines of all possible orientations with respect to a rectangular parallelopiped view volume. The performance of this algorithm has been evaluated using exact arithmetic operation counts. It is shown that our algorithm requires less arithmetic operations than the Cyrus-Beck 3D clipping algorithm in all cases. It is also shown that for lines that intersect the clipping volume, our algorithm performs better than the Liang-Barsky 3D clipping algorithm.

Indian Nanoelectronics Users Program An Outreach Vehicle to Expedite Nanoelectronics Research in India

The worldwide research in nanoelectronics is motivated by the fact that scaling of MOSFETs by conventional top down approach will not continue for ever due to fundamental limits imposed by physics even if it is delayed for some more years. The research community in this domain has largely become multidisciplinary trying to discover novel transistor structures built with novel materials so that semiconductor industry can continue to follow its projected roadmap. However, setting up and running a nanoelectronics facility for research is hugely expensive. Therefore it is a common model to setup a central networked facility that can be shared with large number of users across the research community. The Centres for Excellence in Nanoelectronics (CEN) at Indian Institute of Science, Bangalore (IISc) and Indian Institute of Technology, Bombay (IITB) are such central networked facilities setup with funding of about USD 20 million from the Department of Information Technology (DIT), Ministry of Communications and Information Technology (MCIT), Government of India, in 2005. Indian Nanoelectronics Users Program (INUP) is a missionary program not only to spread awareness and provide training in nanoelectronics but also to provide easy access to the latest facilities at CEN in IISc and at IITB for the wider nanoelectronics research community in India. This program, also funded by MCIT, aims to train researchers by conducting workshops, hands-on training programs, and providing access to CEN facilities. This is a unique program aiming to expedite nanoelectronics research in the country, as the funding for projects required for projects proposed by researchers from around India has prior financial approval from the government and requires only technical approval by the IISc/ IITB team. This paper discusses the objectives of INUP, gives brief descriptions of CEN facilities, the training programs conducted by INUP and list various research activities currently under way in the program.

Centers of Excellence in Nanoelectronics in India

Nanoelectronics is considered an emerging area all over the world and is widely anticipated to hold the key to the future electronic innovations. Realizing its importance, the Government of India has set up two Centers of Excellence in Nanoelectronics (CEN) one at Indian Institute of Science (IISc), Bangalore and the other at Indian Institute of Technology Bombay (IITB) in 2006. The first phase of this program is going to be over in December 2010 and the second phase is going to continue. This paper discusses the objectives of the project, activities, research areas, students training, various research activities, Incubation and Entrepreneurship activity, and interaction with Academic institutions / industries both at National and International level.