Demonstration of Closed Circuit TV by filming Wiliam C. H. Meyer in an Automotive classroom at the New York Trade School

Depiction of closed circuit TV students at the New York Trade School filming a voltage regulator check performed by William C. H. Meyer. Original caption reads, "Closed-circuit TV takes a class at the New York Trade School into the Automotive Shop where William C. H. Meyer, head of the Automotive Department, demonstrates a voltage-regulator check. Students Robert Niefeld (left) and Denis Mahoney serve as cameramen." Black and white photograph part of series of four photographs accompanying a press release of the New York Trade School announcing the demonstration of a new technique in closed-circuit TV developed at the New York Trade School.

Student at work with closed-circuit TV

A student in the Closed-circuit TV Dept. at the New York Trade School is shown working. Black and white photograph.

Closed-circuit Television Student Working

A student is show working with closed-circuit television at the New York Trade School. Black and white photograph.

Classroom of students watching demonstration of closed-circuit TV

Students watch monitors that show a voltage meter being filmed in the Automotive Dept by department head William C. H. Meyer as part of a demonstration of a new technique in closed-circuit television. This is one of a series of photographs accompanying a press release about the development and demonstration of the new technique at the New York Trade School. Original caption reads, "In a classroom on another floor, students all have "front row" seats for the demonstration. Camera concentrates on close-up of a meter, where readings show the result of the voltage-regulator check. Instructor (standing at microphone) is Arthur Richards." Black and white photograph with accompanying caption.

Student Joseph Germer at microphone at closed-circuit TV demonstration

This is one of a series of photographs accompanying a press release by the New York Trade School announcing the development and demonstration of a new technique in closed-circuit TV. In this work student Joseph Germer asks a question about the demonstration. Original caption reads, "Microphone goes to student Joseph Germer, who asks a question about another phase of the demonstration." Black and white photograph with caption.

Closed-circuit Television Students Film a Voltage-regulator check by William C.H. Meyers

One of a series of photographs accompanying a press release by the New York Trade School announcing the development and demonstration of a new technique in closed-circuit TV. Student Dennis Mahoney serves as one of the cameramen as William C. H. Meyers of the Automotive Department performs the demonstration. Black and white photograph.

Contribuição para o estudo do embarque de uma rede neural artificial em field programmable gate array (FPGA)

This study shows the implementation and the embedding of an Artificial Neural Network (ANN) in hardware, or in a programmable device, as a field programmable gate array (FPGA). This work allowed the exploration of different implementations, described in VHDL, of multilayer perceptrons ANN. Due to the parallelism inherent to ANNs, there are disadvantages in software implementations due to the sequential nature of the Von Neumann architectures. As an alternative to this problem, there is a hardware implementation that allows to exploit all the parallelism implicit in this model. Currently, there is an increase in use of FPGAs as a platform to implement neural networks in hardware, exploiting the high processing power, low cost, ease of programming and ability to reconfigure the circuit, allowing the network to adapt to different applications. Given this context, the aim is to develop arrays of neural networks in hardware, a flexible architecture, in which it is possible to add or remove neurons, and mainly, modify the network topology, in order to enable a modular network of fixed-point arithmetic in a FPGA. Five synthesis of VHDL descriptions were produced: two for the neuron with one or two entrances, and three different architectures of ANN. The descriptions of the used architectures became very modular, easily allowing the increase or decrease of the number of neurons. As a result, some complete neural networks were implemented in FPGA, in fixed-point arithmetic, with a high-capacity parallel processing

Bifurcation Analysis of a Van der Pol-Duffing Circuit with Parallel Resistor

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Validation of the SenseWear armband in circuit resistance training with different loads

The use of the SenseWear (TM) armband (SWA), an objective monitor of physical activity, is a relatively new device used by researchers to measure energy expenditure. These monitors are practical, relatively inexpensive and easy-to-use. The aim of the present study was to assess the validity of SWAs for the measurement of energy expenditure (EE) in circuit resistance training (CRT) at three different intensities in moderately active, healthy subjects. The study subjects (17 females, 12 males) undertook CRT at 30, 50 and 70% of the 15 repetition maximum for each exercise component wearing an SWA as well as an Oxycon Mobile (OM) portable metabolic system (a gold standard method for measuring EE). The EE rose as exercise intensity increased, but was underestimated by the SWAs. For women, Bland-Altman plots showed a bias of 1.13 +/- A 1.48 METs and 32.1 +/- A 34.0 kcal in favour of the OM system, while for men values of 2.33 +/- A 1.82 METs and 75.8 +/- A 50.8 kcal were recorded.

A multisampling time-domain CMOS imager with synchronous readout circuit

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Winner-take-all circuit using CMOS technology

In this paper is presented an implementation of winner-take-all circuit using CMOS technology. In the proposed configuration the inputs are current and the outputs voltage. The simulation results show that the circuit can be a winner if its input is larger than the other by 2 mu A. The simulation also shows that the response time is 100ns at a 0.2pF load capacitance. To demonstrate the functionality of the proposed circuit, a two-input winner take all circuit was built and tested by using discrete CMOS transistor array (CD40071).

Arithmetic fuchsian groups and space time block codes

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Circuit board accident - organizational dimension hidden by prescribed safety

This study analyzes an accident in which two maintenance workers suffered severe burns while replacing a circuit breaker panel in a steel mill, following model of analysis and prevention of accidents (MAPA) developed with the objective of enlarging the perimeter of interventions and contributing to deconstruction of blame attribution practices. The study was based on materials produced by a health service team in an in-depth analysis of the accident. The analysis shows that decisions related to system modernization were taken without considering their implications in maintenance scheduling and creating conflicts of priorities and of interests between production and safety; and also reveals that the lack of a systemic perspective in safety management was its principal failure. To explain the accident as merely non-fulfillment of idealized formal safety rules feeds practices of blame attribution supported by alibi norms and inhibits possible prevention. In contrast, accident analyses undertaken in worker health surveillance services show potential to reveal origins of these events incubated in the history of the system ignored in practices guided by the traditional paradigm.